Multilevel resistive switching memory based on GO/MoS2/GO stack AsiaNano 2016 2P-017 Gwang Hyuk Shin1,2, Choong-Ki Kim1, Gyeong Sook Bang1,2, Byung Chul Jang1,2, Myung Hun Woo1,2, Yang-Kyu Choi1 and Sung-Yool Choi1,2 1School of Electrical Engineering KAIST, Korea and 2Graphene Research Center, KAIST, Korea ABSTRACT We demonstrated a multilevel resistive switching memory based on the device geometry of graphene oxide (GO) / MoS2 / (GO). This stack was successfully fabricated by simple spin-coating solution process. The device shows suitable multilevel memory performance including at least 104 retention times and over 100 switching endurance cycles. Furthermore, switching mechanism could be attributed to the space charge limited conduction (SCLC). I. Introduction III. Results & Analysis Fig.3. An excellent multilevel switching characteristics. [7] Current (A) Voltage (V) Time (s) Input voltage Output current Resistive switching memory is one of the promising candidates for the next generation non-volatile memory due to its simple fabrication process as well as outstanding memory performance including fast switching speed and low power consumption [1-3]. As a strategy for maximizing information storage density, the multilevel cell (MLC) devices have been extensively studied in the past decades such that the MLCs of resistive switching memory has been reported from various materials, such as polymers and binary metal oxides [4-6]. However, there only exists few study of the MLC operation based on only two dimensional (2D) materials. References [1] Hwang, C. S. et al., Adv. Electron. Mater., 1, 1400056 (2015). [2] Jeong, D. S. et al., Rep. Prog. Phys., 75, 076502 (2012). [3] Yang, J. J. et al., Nat. Nanotechnol., 3, 429-433 (2008). [4] Yoon, J.H. et al., Adv. Mater., 27, 3811-3816 (2015). [5] Choi, S.J. et al., Adv. Mater., 11, 3272-3277 (2011). [6] Hwang, S.K. et al, Nano Letter, 12, 2217-2221. [7] Shin, G. H. et al., 2D Mater., 3, 034002 (2016). 10-3 10-4 00 00 10-5 01 10-6 10 10-7 11 10-8 4.0 At -0.2 V 4.0 V 3.7 V 3.5 3.5 V 3.0 -4 -4.0 V -4.0 V 10 20 30 40 50 60 Multilevel switching characteristic was demonstrated by discrete input bias with SET voltage of -4V and RESET voltage of 3.5V, 3.7V, and 4.0V. Bottom Voltage-time plot represents the input voltage scheme. Top Current-time plot shows the measured output current Current states was decoded by 00, 01, 10, 11 indicating 2-bits operation in a cell. Current (A) Voltage (V) 10-12 10-10 10-8 10-6 10-4 10-2 -4 -2 2 4 3.5 V 3.7 V 4 V SET process 1st RESET 2nd RESET 3rd RESET (a) (b) Au GO MoS2 (a) (b) Fig. 4. The device reliability of the retention time and endurance characteristics. [7] 109 At -0.2 V HRS At -0.2 V HRS 108 IRS1 IRS 11 IRS2 LRS 108 107 Al 10 Resistance (Ω) Resistance (Ω) 100x 106 107 01 105 00 106 104 Fig.1. Typical multilevel I-V curve of Au/GO/MoS2/GO/Al memory. [7] Figure (a) shows the illustration of the device structure. In the Figure (b) Inset figure shows the schematic diagram of 5 x 5 cross-bar array of our device. Multilevel was realized by controlling the maximum voltage of RESET in negative differential resistance region (NDR). 5x103 104 20 40 60 80 100 Time (s) Cycle number (#) II. Device Fabrication Process Stable retention time over 104 s and endurance cycles over 102 times. (a) (b) (a) (b) (c) (d) Slope ∼ 2 Slope ∼ 2 2.46 eV 10-4 Slope ∼ 1 Slope ∼ 1 4.28 eV Slope ∼ 9 Slope ∼ 10 Current (A) 10-6 Slope ∼ 2 Slope ∼ 1 Slope ∼ 1 Slope ∼ 2 10-8 5.53 eV SET region RESET region Negative bias Positive bias 1 0.1 0.01 0.1 1 Voltage (V) Fig. 5. The energy band diagram of the device (a) and double logarithmic I-V plot (b). [7] Switching mechanism was revealed by space charge limited conduction. IV. Conclusion In conclusion, we fabricated a multilevel resistive switching memory based on 2D nanomaterials of GO and MoS2. The stack of GO/MoS2/GO results in suitable memory characteristics. Furthermore, switching mechanism was revealed as the space charge limited conduction. Fig. 2. Characterization of the device. Figure (a), (b), and (c) show a SEM image, EDS spectrum, and AFM image of spin-coated MoS2 on GO thin film. Figure (d) represents a cross-sectional TEM image of the device. [7] We fabricated the stacks of GO/MoS2/GO using only spin-coating process. Figure (a) shows the SEM image with back scattered electron mode. At white spot in SEM image, the MoS2 was detected as shown in Figure (b). The thickness of MoS2 nanosheet was about 3nm as shown in AFM line profile plot. Figure (d) exhibits the cross-sectional bright field TEM image of the device. Acknowledgements We acknowledge the financial supports from Global Frontier Research Center for Advanced Soft Electronics (2011-0031640), the Creative Research Program of the ETRI (13ZE1110). MNDL (Molecular & Nano Device Lab.), School of Engineering and Graphene Research Center, KAIST 291 Daehak-ro, Yuseong-gu, Daejeon, 305-701, Korea *E-mail : sungyool.choi@kaist.ac.kr Phone:+82-42-350-7627, 3477 Fax:+82-42-350-7283