University of California Los Angeles ALCT and TMB Status Martin von der Mey University of California Los Angeles Mezzanine board production status ALCT384 production status ALCT672 and ALCT288 status TMB status Electronics integration at UCLA FAST site

Power, computer connectors ALCT384 Boards Power, computer connectors 80 MHz SCSI outputs (to Trigger Motherboard) Xilinx Mezz. board 24 Input signal connectors Delay/ buffer ASICs, 2:1 bus multiplexors (other side) Analog section: test pulse generator, AFEB power, ADCs, DACs (other side) Spartan XL

Mezzanine Board Status All FPGAs were purchased. 462 XCV600E. 112 XCV1000E. 543 mezzanine boards were initially produced and assembled (431 XCV600E, 112 XCV1000E). Replaced 150 bad EPROMs on mezz. Boards. Some mezz. Boards need reassemble of FPGA. Shorts between neighbor pins. Pins not connected

ALCT Production Testing Using 3 stations. 2 for testing. 1 for fixing. 2 shifts per day Crew of 6 students testing. 2 students helping Valeri Iatsura with fixing. Add serial number to database. Update database with problems.

Testing Board

Problems Encountered Most frequent problems: Delay chips have shorts. Some replaced Shorts at bus multiplexer Different components. Wrong part numbers Rotated and broken chips. Shorts and broken wires inside PCB. Seldom problems with delay chips after burn-in. Few problems with Slow Control Eprom. (replace)

ALCT-384 Status All 250 ALCT384 boards were received. 170 fully tested before and after 2 day x 70oc burn-in. 12 boards still require repair. 80 boards still need to be tested. More than enough boards for shipping to FAST sites. 90 shipped to UCLA and UFL FAST sites already. 30 ready for shipping to IHEP. Have parts for all boards including -672, -288 varieties.

ALCT-672 and ALCT-288

ALCT-672 and ALCT–288 Assembly of 28 boards of ALCT-672, 6 of ALCT-288 All 123 ALCT-672 and 170 ALCT-288 PC boards delivered. Assembly of 28 boards of ALCT-672, 6 of ALCT-288 ALCT-672: 3 to PNPI, 16 at UF, 9 at UCLA to be tested or fixed ALCT-288: 3 to IHEP, 1 at UF, 1 at FNAL, 1 at UCLA Ordered the remainder of 63 ALCT-672 boards Ordered a pre-production batch of 22 out of remaining 159 ALCT-288 for assembly. UFL FAST site tests showed good performance of ALCT-672 and ALCT-288. 14 ALCT-672 have been shipped to FNAL for on-chamber testing and then shipment to PNPI. Expect first batch of 22 ALCT-288 in 2 weeks. After approval of assembly job all will be assembled.

Problems found (FAST) 11 problem boards Previously seen problems: ALCT was sending wrong standby patterns. ALCT loaded with wrong FPGA firmware. ALCT was noisy. One of the test pulse outputs was always enabled. ALCT displayed wrong temperature and current. Problem with ADCs. Connectors improperly soldered. New problems: Strange response of any AFEB if plug in connector #8. (can’t reproduce) Bad test pulse to all AFEBs. Couldn’t load 4 boards using svf files. (can’t reproduce).

Trigger Motherboard (TMB) Input connectors From ALCT Main FPGA (on back) XILINX XCV1000E Mezzanine board From 5 CFEB’s Generates Cathode LCT trigger with input from CFEB (comparator) Matches ALCT and CLCT; sends trigger primitive info via MPC to Lev-1 muon trigger, sends anode and cathode hits to DMB.

TMB Integration at UCLA FAST Site Full set of peripheral crate electronics: TMB with DMB, CCB DDU readout through Gbit Ethernet to Linux PC Also full set of AFEB, CFEB, ME2/2 chamber Debug whole DAQ readout Time in DAQ system Debug trigger modes Debug new functionalities Debug new DDU prototype

TMB Prototype Status 18 boards assembled and working. Full set of bench tests. Testing board built to check inputs and outputs (VME backplane). Received 3 bad TMBs back from UFL. Tests in progress. Next set of tests at UCLA with OSU this and next week. Goals: Integration of the whole system Full set of trigger patterns DDU readout (TTCrx) Separate ALCT and TMB data streams to DMB High-rate tests Multi chamber and multi crate readout

TMB Future Plans (Hardware) Real peripheral crates will require a transition module in back to receive signals from ALCT and RPC cables. Virtex-II mezzanine card were produced to replace Virtex-E. Produced small PC board for Data Delay Devices chip to replace PHOS4. Increase TMB-to-DMB data path from 15 to 30 bits wide. Agreement with OSU on backplane pins and signal assignments.

PHOS4 Replacement New Delay chips TMB uses PHOS4 chips for adjusting 10 clock delays (CFEBs, ALCT, DMB and RPC). Trying out Data Delay Devices (3D3444). Each has 4 channels  PHOS4 5 channels => 3 chips necessary to replace 2 PHOS4 chips. They have (16x2.0ns) and (16x1.5ns). First test (2.0ns) duty cycle 68/32 for data sent from CFEB to TMB New Delay chips

TMB Firmware Changes Future improvements: Changes made : Added DiStrip and multiple patterns. DMB pre-trigger can pre-trigger on ½-Strip or DiStrip. Independent thresholds for ½-Strip and DiStrips. Replace PHOS4 chips. New firmware necessary. Already done. Changes in progress (debugging) : Add DAQ multi-buffer handling capability. Future improvements: Add RPC coincidence logic. Useful to solve ambiguities. Virtex-II FPGA faster by 50% for same cost (XC2V3000 or XC2V4000)

TMB firmware changes Trigger Sequencer: Now includes Gilmores random active-feb-vector mode Can require ALCT coincidence to pre-trigger (may not be possible to time-in) Control signals to Buffer Manager for writing raw hits. Stores CLCT data in distributed RAM (no LUTs anymore) Not yet timed in with CFEB module and TMB module.

TMB firmware changes (OSU) CLCT raw hits multi-buffering, 8 events CFEB section done New Buffer manager code works for writing Write timing not yet tuned Readout section incomplete Special mode to send random active_feb_flag bits to DMB (when triggered).

TMB firmware changes Added special mode where CLCT pre-trigger always results in L1A request. Local Dump reads out only hit CFEBs Add CRC to TMB data stream. CRC calculator done Not yet integrated with readout data

TMB Logic for tests Proposal for tests this week: Modify 1 TMB circuit board to work with new DMB backplane signals Use TMB logic from FAST site version and change ALCT backplane signals Allows to test TMB with modified DMB High rate test possible

CSC Event Display (Brian Mohr)

CSC Event Display

CSC Event Display

CSC Event Display

CSC Event Display

CSC Event Display

CSC Display Status Added best muon track from TMB Compiled version available. Runs 10x faster. Compiled version now available from CMS CVS repository. Modified display window to display similar information to current FAST site software Update to read DDU output Add multiple chamber capability How to display (several windows?)

TMB Readout and Simulation of Throughput Hardware: ALCT data now goes directly to a separate DMB FIFO (change) ME1/1 Worst Case Simulation result for CLCT readout: 10% of LCTs read out (versus 3% expected) 8 buffers

Conclusions ALCT production in excellent shape. Production of ALCT-672,-288 ongoing. Testing working fine. Some problems can’t be prevented. TMB firmware in progress. Many changes implemented. New tests on the way next week with OSU toward full integration of the system.