Partial Evaluation Based Redundancy for SEU Mitigation in Combinational Circuits MAPLD 2005 BOF-L Mitigation Methods for Reprogrammable Logic in the Space Radiation Environment Sujana Kakarla & Srinivas Katkoori {kakarla, katkoori}@cse.usf.edu Computer Science & Engineering University of South Florida

Partial Evaluation Based Triple Modular Redundancy Observation If some input values are known in advance The entire circuit need not be triplicated Gates with constant output can be eliminated Functionally equivalent reduced circuit is obtained Triplicate the reduced circuit

Partial Evaluation Functional level Partial Evaluation Widely used in the software applications Not popular in hardware because of its static nature Optimization by exploiting prior knowledge Functional level Partial Evaluation Propagate known values throughout the function Obtain new specialized function Done at run time Techniques: Symbolic computation, Loop unrolling, Memoization, etc., Advantages: Speed up Efficient and modular solution

Temporal TMR Majority voter circuit for T-TMR Original circuit Final output delay unit delay unit Majority voter circuit for PE Reduced circuit select line Reduced circuit Logic for select line of multiplexer Spatial TMR

Need for Temporal TMR Temporal TMR is used in cases when the actual inputs to the circuit are not in accordance with the rounded values A = 0.124 A ‘rounded’ to 0 B = 0.46 C = 0.84 B = 0.46 0.3864 C = 0.84 A = 0 B = 1 C = 0 Out = 0 A = 0 B = 1 C = 0 Out = 0 A = 1 B = 1 C = 0 Out = 1 A = 1 B = 1 C = 0 Out = 0 Incorrect Output!

Temporal TMR Circuit Voter circuit Delay Unit Delay Unit

Partial Evaluation TMR Flow Step 1 Rounding probabilities Step 5 Determine output from Temporal TMR circuit Step 2 Propagate probabilities Resolve logic on signals Step 6 Selection of output from the two sets of values Step 3 Obtain functionally equivalent reduced circuit Step 7 Validation Step 4 Determine output from Partially evaluated circuit

Step 1: Rounding the probabilities If the input probabilities are such that 0.0 ≤ p ≤ 0.2 => logic value = ‘0’ 0.9 ≤ p ≤ 1.0 => logic value = ‘1’ The rounded probability values are then propagated over the circuit

Step 2: Propagate Probabilities Type of Gate Output probability AND NAND OR NOR XOR XNOR

Step 3: Redundant gate elimination All redundant gates are eliminated “not” gate cannot be eliminated Gates in the last level cannot be eliminated

Step 4: TMR Insertion The reduced circuit is duplicated A majority voter is used at each output Original Circuit Majority Voter Circuit Reduced Circuit Correct output Reduced Circuit

Step 5: Temporal TMR For temporal TMR, pass each of the output through a series of two delay units We now have the output determined at three instances of time A majority voter is used to determine the correct output Majority Voter Circuit Correct output Original Circuit Delay unit Delay unit

Step 6: Output Selection Two sets of output values, one set from partial evaluation based TMR the other from Temporal TMR Multiplexer selects the correct output among the two sets Suppose probability of input A, p is such that 0.9 ≤ p ≤ 1.0 probability of input B, q is such that 0.1 ≤ q ≤ 0.2 then the select line for the multiplexer is Ā + B

Step 7: Validation Original circuit Faults representing SEUs are introduced into the circuit using a SEU simulator Faulted circuit is functionally verified using NC Cadence Launch Outputs of the original circuit without faults and outputs of the faulted circuit are compared to check if any fault has propagated to the output Implementation of partial evaluation Reduced circuit SEU Simulator Simulate original circuit Simulate faulted circuit Comparison Results

Advantages and Disadvantages of Partial Evaluation based TMR Less area overhead Power savings High tolerance to SEUs Disadvantages In the worst case, area overhead is greater than the full TMR Delay overhead when Temporal TMR is used Spatial TMR Area overhead Temporal TMR Delay overhead PE based TMR

Experimental Results Name of the circuit Total number of gates Number of redundant gates Total number of outputs % of redundant gates A TMR – A PE A TMR (as percentage) X3 706 402 99 56.9 46.9 Cm150a 58 41 1 70.6 34.26 Alu2 335 207 5 61.9 34.04 9symml 166 92 55.42 32.47 alu4 674 371 6 55 32.25 Count 105 62 59 31.66 I2 161 84 52.17 30.18 Mux 79 53.16 26.14 C432 209 108 4 51.6 24.19 Frg1 100 3 23.39 Cordic 64 38 2 59.3 21.1 term1 364 167 9 45.87 20.83 I4 154 82 53.24 18.1 I3 106 66 62.26 16.37 Too_large 342 50.74 31.5

Experimental Results Contd., Name of the circuit Total number of gates Number of redundant gates Total number of outputs % of redundant gates A TMR – A PE A TMR (as percentage) F51m 123 73 7 59.3 14.86 Vda 805 403 39 50 13.4 Cmb 43 29 4 67.44 12.4 C880 317 197 24 62.73 11.46 C2670 677 314 34 46.38 11.25 Z4ml 52 36 69.23 10.46 Cm85a 32 22 3 68.75 10.18 Cm151a 20 1 68.9 9.8 Cm152a 23 13 56.52 9.5 I9 757 470 63 52.08 9.3 X1 307 203 28 66.12 8.77 C1908 398 190 25 47.7 7.3 Parity 15 9 60.5 6.1 Ttt2 204 133 21 65.19 3.5 My_adder 146 100 17 68.49 0.59

Experimental Results Contd., Name of the circuit Total number of gates Number of redundant gates Total number of outputs % of redundant gates A TMR – A PE A TMR (as percentage) *c8 162 98 17 62.3 -0.1 *cm162a 44 31 5 70.45 -0.6 *cm163a 43 32 69.76 -3.3 *i7 552 236 67 43.11 -14.1 *x4 439 224 65 51.02 -17.5

PTMR - Conclusions Greater savings in area are obtained for circuits with more number of gates and with less number of primary outputs The area overhead for the technique is proportional to the number of primary outputs Area overhead of PTMR circuit is less than TMR but has greater delay overhead Delay overhead of PTMR is less than Temporal TMR