1. FT-UNSHADES: a new system for SEU injection, analysis and diagnostics over post synthesis netlists
M. Aguirre1, J.N. Tombs1, F. Muñoz1, V. Baena1, A. Torralba1, A. Fernández-León2,, F. Tortosa-López2
1Escuela Superior de Ingenieros Universidad de Sevilla Camino de los Descubrimientos s/n Sevilla (SPAIN)
2Data Systems Division. ESTEC/TOS-ED European Space Agency. Noordwijk (THE NETHERLANDS)

2. MAPLD 2005, Washington (USA)
Summary
Brief Description of FT-UNSHADES project
What is not FT-UNSHADES?
FT-UNSHADES secret: Partial Reconfiguration
The system
Design flow
Tests procedure
Analysis procedure
Benchmarking
Conclusions
The Future
Q&A
MAPLD 2005, Washington (USA)

3. Brief Description of FT-UNSHADES project
Radiation environment emulator
Use a huge FPGA from Xilinx
Initial objective: Provide a test and analysis framework to check the design protections (TMRs and voters, EDACs, …) of an IP or ASIC, BEFORE place and route and fabrication
Current solutions:
VHDL simulators
Instrumenting FFs 1
SEU D Q
MAPLD 2005, Washington (USA)

4. What FT-UNSHADES isn’t?
It’s not a platform for radiation testing of FPGAs
It’s not designed for being inserted into a radiation environment
MAPLD 2005, Washington (USA)

5. FT-UNSHADES secret: Xlinx partial reconfiguration
Takes advantage of partial reconfiguration techniques for fault injection and capture and readback for design observation
Changes in FF state are made from the configuration circuit. Netlist does not need to be modified to pass FT-UNSHADES fault-injection tests.
Direct manipulation of bitstream slices speeds-up the bit-flip induction.
Large circuits with huge stimulus vector database are tested at hardware speed
CIRCUIT IS TREATED AS A BLACK BOX
MAPLD 2005, Washington (USA)

6. System elements: the board
Vector
Memories
2Mx102
Multi
Board Link
SYSTEM FPGA
Virtex II
Control FPGA
Spartan II-50
PC-Host
USB Link
MAPLD 2005, Washington (USA)

7. MAPLD 2005, Washington (USA)
System elements: the software
TNT
INPUT VECTOR DATABASE
BITSTREAM
BIT ALLOCATION
User
Commands
(Scripts)
WAVEFORM
Session.log
Excel Sheet
Console
MAPLD 2005, Washington (USA)

8. MAPLD 2005, Washington (USA)
Test Model
Two identical instances
of the Module Under Test
are synthesised with the
Test Shell:
-SEU_MUT receives the
bit flips
-GOLD_MUT allows
comparisons
Both MUTs must be treated
as Macros, to avoid their
synthesis collapsing.
Test Shell:
-R/W the memories
-Controls the clock
-Reports events
-Controls the display
MAPLD 2005, Washington (USA)

9. MAPLD 2005, Washington (USA)
Design flow
MAPLD 2005, Washington (USA)

10. Test Procedure: When, Where and How
Configure the System FPGA and download the input vector database
Specify the test level (How):
Damage
Output
Latent
Specify time (When)
Specify location (Where)
Specify method and conditions (How)
RUNTEST <- Fault Dictionary is generated
MAPLD 2005, Washington (USA)

11. MAPLD 2005, Washington (USA)
A single test process:
SEU(T,L)
A single test run has the following schedule:
Program the time counter with T
Give Module Reset
Launch the system to stop at T
Get frames related to L
Induce SEU at L
Resume system
Watch events to check SEU effects.
MAPLD 2005, Washington (USA)

12. MAPLD 2005, Washington (USA)
Analysis Procedure:
Step: Run a single clock cycle and check internal evolutions
AnRun Command: Run the emulation to the insertion point. Then analyse.
Diff command: Compare the states of Gold/SEU instances to check internal propagation
MAPLD 2005, Washington (USA)

13. MAPLD 2005, Washington (USA)
Benchmarking
MAPLD 2005, Washington (USA)

14. MAPLD 2005, Washington (USA)
Conclusions
Circuit Overhead: system gates
Fault injection time: 0,8ms (XC2V6000) and 0,9ms (XC2V8000)
A tool for verification of your design protections
Automatic search of weak/unprotected points
Understand/reproduce rad test results
Analysis
Non-intrusive controlled (Time,Location) SEU injection
If you want to reduce the protection level … or optimize critical areas
MAPLD 2005, Washington (USA)

15. MAPLD 2005, Washington (USA)
Future of FT-UNSHADES
Large circuit benchmarking (Leon2)
Output files for automatic TMR insertion tools, in order to produce selective protection
Test with multi SEUs
Improve system performance
Extend the injections to memory blocks
MAPLD 2005, Washington (USA)

16. Thank you for your attention
Q&A
MAPLD 2005, Washington (USA)