Downsizing Semiconductor Device (MOSFET)

Slides:



Advertisements
Similar presentations
MOS Capacitors MOS capacitors are the basic building blocks of CMOS transistors MOS capacitors distill the basic physics of MOS transistors MOS capacitors.
Advertisements

Device Physics – Transistor Integrated Circuit
Introduction to FinFet
Device EE4271 VLSI Design Dr. Shiyan Hu Office: EERC 518
HO #3: ELEN Review MOS TransistorsPage 1S. Saha Long Channel MOS Transistors The theory developed for MOS capacitor (HO #2) can be directly extended.
Introduction to CMOS VLSI Design Lecture 0: Introduction.
1 Models for Hand Analysis NMOS Transistor PMOS Transistor V DSN  V GSN -V TN V DSN  V GSN -V TN V DSP  V GSP -V TP V DSP  V GSP -V TP K N =(W/L)K’
The Devices: MOS Transistor
UNIT II : BASIC ELECTRICAL PROPERTIES
Smruti R. Sarangi IIT Delhi
MOSFET The MOSFET (Metal Oxide Semiconductor Field Effect Transistor) transistor is a semiconductor device which is widely used for switching and amplifying.
Field Effect Transistors: Operation, Circuit Models, and Applications
MOS Field-Effect Transistors (MOSFETs)
Floating-Gate Devices / Circuits
Field-Effect Transistors Based on Chapter 11 of the textbook
Digital Electronics Class Lecture October 22, 2008
VLSI design Short channel Effects in Deep Submicron CMOS
Lecture 21 OUTLINE The MOSFET (cont’d) P-channel MOSFET
Introduction to Metal-Oxide-Semiconductor Field Effect Transistors (MOSFETs) Chapter 7, Anderson and Anderson.
Hot Chips, Slow Wires, Leaky Transistors
Lecture 22 OUTLINE The MOSFET (cont’d) MOSFET scaling
3: CMOS Transistor Theory
VLSI Design MOSFET Scaling and CMOS Latch Up
EE141 Chapter 3 VLSI Design The Devices March 28, 2003.
ENG2410 Digital Design “CMOS Technology”
IC TECHNOLOGY.
CMOS circuits and Logic families
MOSFET Scaling ECE G201.
Lecture 22 OUTLINE The MOSFET (cont’d) Velocity saturation
An Illustration of 0.1µm CMOS layout design on PC
Lecture 16 ANNOUNCEMENTS OUTLINE MOS capacitor (cont’d)
Lecture 19 OUTLINE The MOSFET: Structure and operation
منبع: & کتابMICROELECTRONIC CIRCUITS 5/e Sedra/Smith
Digital Integrated Circuits 10: Short-Channel MOSFETs
Optional Reading: Pierret 4; Hu 3
Device Physics – Transistor Integrated Circuit
Qualitative Discussion of MOS Transistors
VLSI Design CMOS Transistor Theory
MOSFET Scaling ECE G201.
Downsizing Semiconductor Device (MOSFET)
ELEC 6970: Low Power Design Class Project By: Sachin Dhingra
MOSFET POWERPOINT PRESENTATION BY:- POONAM SHARMA LECTURER ELECTRICAL
Prof. Hsien-Hsin Sean Lee
FIELD EFFECT TRANSISTOR
CSV881: Low-Power Design Power Dissipation in CMOS Circuits
Lecture 19 OUTLINE The MOS Capacitor (cont’d) The MOSFET:
Lecture 21 OUTLINE The MOSFET (cont’d) P-channel MOSFET
Chapter 9: Short channel effects and
EMT 182 Analog Electronics I
Device EE4271 VLSI Design Dr. Shiyan Hu Office: EERC 731
Device Physics – Transistor Integrated Circuit
CP-406 VLSI System Design CMOS Transistor Theory
EXAMPLE 7.1 BJECTIVE Determine the total bias current on an IC due to subthreshold current. Assume there are 107 n-channel transistors on a single chip,
Lecture 22 OUTLINE The MOSFET (cont’d) MOSFET scaling
Lecture 19 OUTLINE The MOS Capacitor (cont’d) The MOSFET:
Lecture 22 OUTLINE The MOSFET (cont’d) Velocity saturation
Thermal Modeling for Modern VLSI Circuits
Lecture #15 OUTLINE Diode analysis and applications continued
Lecture 3: CMOS Transistor Theory
Reading (Rabaey et al.): Sections 3.5, 5.6
Technology scaling Currently, technology scaling has a threefold objective: Reduce the gate delay by 30% (43% increase in frequency) Double the transistor.
Lecture 3: CMOS Transistor Theory
Lecture 4: Nonideal Transistor Theory
Ideal Scaling of MOSFETs
Overview of Course Goal: Primarily to develop techniques and intuition for evaluating and understanding digital (and analog) circuits, and especially.
Copyright © 2004 The McGraw-Hill Companies, Inc. All rights reserved.
Lecture #16 OUTLINE MOSFET ID vs. VGS characteristic
Beyond Si MOSFETs Part 1.
Dr. Hari Kishore Kakarla ECE
Presentation transcript:

Downsizing Semiconductor Device (MOSFET) EMT 251

Downsizing Device

Downsizing Device Downsizing of semiconductor devices (MOSFET/CMOS) More transistors can be fabricated into single chips. G-Shock Combination Wristwatch (Fujitsu/Flash memory @ 0.5 mm pitch by IEP Technologies) MSI (medium) LSI (large) VLSI (very large) ULSI (ultra large scale integration) SCALING DEVICES!!

SCALING DEVICE Original Device Scaled Device n+ Volt, V Wiring tox W Gate Wiring W XD LG n+ tox p-Substrate, Doping = NA Volt, V W/ LG/ tox/ p-Substrate, Doping = NA V/

Scaling Technique Scaling of MOSFET device and circuit parameters Constant-field scaling (Full scaling) Constant-voltage scaling Device dimension (tox, L, W,Xj ) 1/S Power supply voltage (VDD) 1 Electric field (E) S Threshold voltage (VT) Doping density (NA,ND) S2 Drain current (Id) Oxide capacitance (Cox) Capacitance (C) Circuit delay time ( τ ) 1/S2 Power dissipation (P) Power delay (Pτ) 1/S3 Power density (P/A) S3 Sheet resistance (R) Scaling of MOSFET device and circuit parameters

STANDARD PARAMETERS PUBLISHED BY ITRS SIZE LG(µm) TOX(nm) VTH NMOS PMOS 180nm 0.18±15% 4.2±4% 0.40±12.7% -0.42±12.7% 130nm 0.13±15% 3.3±4% 0.34±12.7% -0.35±12.7% 100nm 0.10±15% 2.5±4% 0.26±12.7% -0.30±12.7% 70nm 0.07±15% 1.7±4% 0.20±12.7% -0.22±12.7%

Example 150nm 0.15 ±15% SIZE LG(µm) TOX(nm) VTH NMOS PMOS 180nm 0.18±15% 4.2±4% 0.40±12.7% -0.42±12.7% 150nm   0.15 ±15%   ? 130nm 0.13±15% 3.3±4% 0.34±12.7% -0.35±12.7% 100nm 0.10±15% 2.5±4% 0.26±12.7% -0.30±12.7% 70nm 0.07±15% 1.7±4% 0.20±12.7% -0.22±12.7%

Example (cont…) VTH NMOS=0.3642 VTH PMOS=-0.3849

Example (cont…) NMOS PMOS Complete CMOS Structure

Example (cont…) Id - Vd NMOS PMOS Id - Vg

Advantages of MOSFET/CMOS downsizing High Integration High Speed Operation Decrease the Switching Time of the Transistor Low Cost Low Power Consumption CMOS has the lowest power consumption! Complementary nature of PMOS and NMOS

Scaling Limitation Factors Short channel effect (SCE) Drain-Induce Barrier Lowering (DIBL) Bulk Punch-trough Hot Electron Effect Extra Notes!!

THE END