Synopsys PrimeTime

Introduction Static Timing Analysis tool Static Timing Analysis : Determines whether the design works at the required speed.

PrimeTime ASIC design from Design Compiler PrimeTime Timing performance and violation report or Layout Verilog from IC Compiler Design Constraints Rise/Fall Time Gate delay

PrimeTime Basic Flow set library path read the design set search_path set link_path read the design read_verilog link library and the design link add design constraints read_sdc add constant value to input port (for timing simulation) set_case_analysis report report_constraint report_timing

Constraints File Example

Timing report

PrimeTime GUI

GUI - Timing Path

GUI – Timing Inspection

Tutorial Sources http://read.pudn.com/downloads157/sourcecode/embed/701548 /PrimeTime_Intro_to_STA/print_materials/PTISTA_lab1_flow.p df http://userwww.sfsu.edu/necrc/files/synopsys%20tutorials/ASIC %20Design%20Flow%20Tutorial.pdf