FrontEnd LInk eXchange Proto Dune Data Emulator using: FrontEnd LInk eXchange By: René Habraken

Introduction Adjustments made to FELIX hardware Data Emulator Current status Next steps

configuration registers: control and monitor Stage setting… FELIX Firmware Wupper PCIe engine Central Router Wupper core DMA engine data/TTC encoding, routing, multiplexing DMA toHost fromHost GBT-FPGA wrapper to-Host path from-Host path TTC fmc wrapper TTC Decoder CLK&RST mmcm firmware clocks* TTC clk XILINX PCIe End Point board oscillator DMA control PCIe Gen3 x8 optical connectors Interrupt controller configuration registers: control and monitor Busy TTC data FIFO data demux, alignment, decoding, packet/busy detection, header and packet trailer attachment with N GBT channels House-keeping proc Original felix hardware is modified to felix “light” Stripped off the parts that I did not need like:….

configuration registers: control and monitor Reused parts Data Emulator Firmware Wupper PCIe engine Output Control Wupper core DMA engine create package, header, routing, multiplexing DMA toHost fromHost Transceiver Data return Transmit controller CLK&RST mmcm firmware clocks* XILINX PCIe End Point DMA control PCIe Gen3 x8 optical connectors Interrupt controller configuration registers: control and monitor FIFO ILA with N channels House-keeping 32b Up/Dn Counter FELIX – PC Data generation from user application

Felix Full Mode From: “Specification for the FELIX Full mode link”. Data Emulator FELIX firmware            The specification of the data emulator is taken from the document “Felix Full mode link” and is defined in terms of communication protocol with the existing felix hardware.

Data Emulator Interconnect logic Transmit controller Data Source Transmitter to-FELIX Data Source Optic link to-FELIX The specification for the full mode link

Data Source and Interconnect logic An overview of the new firmware in a bit more detail. The felix pc now on the left side and the transceiver and optical link on the right side. The middle part is wedged between two fifo’s. The one on the left being… The new hardware for the data emulator is a clocked process to deal with the package size and datatype handling. The package size can be set from a control register as well as the dataflow. It is possible to enable the counter for hardware generated data or select the path trough the Wupper and the 256b to 32b fifo. The same process is used for both the counter and the pc generated data so regardless of the source of the data it comes in 120 word packages with the correct datatype bits. The 32bits of the data are combined with the two bits of the data type and buffered in the 34to34b fifo. From that fifo it can be read by the “to felix stream controller” and send by the transceiver over the optical link to the felix hardware.

configuration registers: control and monitor Status: this week Data flow A: Test setup VC709 fiber loopback with ILA (logic analyzer core) Wupper PCIe engine Output Control Wupper core DMA engine create package, header, routing, multiplexing DMA toHost fromHost Transceiver Data return Transmit controller CLK&RST mmcm firmware clocks* XILINX PCIe End Point DMA control PCIe Gen3 x8 optical connectors Interrupt controller configuration registers: control and monitor FIFO ILA with N channels House-keeping 32b Up/Dn Counter FELIX – PC Data generation from user application All the hardware is in place for a loopback test using the ILA to analyse the data being send. The possibility is there to switch between the counter data and the pc. The new hardware of the output control is simulated and the project is successfully build in vivado. Last Thursday however there seemed to be something wrong with the clock setup. The Si5324 clock generator chip did not seem to lock and the transceiver was outputting only random data (in stead of idle char).

Data flow B: from FELIX-PC through one VC709 card and loop back to PC. VC709  data emulator Data flow B: from FELIX-PC through one VC709 card and loop back to PC.

FELIX – PC VC709  Data Emulator VC709  FELIX Full Mode HW Data flow C: two VC709 cards, one being the emulator and the other one the FELIX Full Mode HW.

Next steps Debug loopback with VC709 card and the logic analyzer in FPGA Backup the project in GIT Adjust to multiple links and add timestamp Data flow B: from FELIX-PC through one VC709 card and loop back to PC. Data flow C: two VC709 cards, one being the emulator and one with the standard FELIX full mode HW.

Backup sheets

Data type

FELIX Development Cards (FLX) FLX-710 (FELIX) HiTech Global HTG-710 Virtex-7 X690T PCIe Gen 3 x 8 lanes 2x12 bidir CXP connectors FMC connector FLX-709 (MiniFELIX) Subset of the full FELIX functionality, intended for FE development support Xilinx VC-709 Virtex-7 X690T PCIe Gen 3 x 8 lanes 4 SFP+ connectors FMC connector TTCfx Custom FMC accepting TTC input Outputs TTC clock and CH A-B info V1: ADN2814 + CDCE62005 V2: ADN2814 + Si5338

Data format ProtoDune