Status of the Front-End Electronics and DCS for PHOS and TPC Johan Alme (johan.alme@ift.uib.no) Norwegian CERN committee meeting, 15.-16. Nov 2007, Oslo

Overview Norwegian contributions to ALICE experiment within: Trigger and readout network. Control network Status and publications

Front End Electronics Overview Readout Network Trigger Detectors generate Level 0 and Level 1 triggers. Central Trigger Processor distributes triggers to sub detectors. Front End Electronics start buffering data on L0/L1. Front End Electronics start data readout on L2 if DAQ is ready. The BusyBox tells CTP to stop issuing of triggers if FEE buffers are full.

Trigger OR Vital part of the trigger generation chain of PHOS. Readout Network Vital part of the trigger generation chain of PHOS. Developed in Norway in cooperation between University of Bergen and Bergen University College. Norwegian project student at CERN developing firmware. Also working with Trigger Router Unit (TRU) Currently under test at CERN.

TPC & PHOS Readout Electronics Readout Network

TPC & PHOS Readout Electronics Readout Network Readout Control Unit (RCU) front Nøkkeltall: 36 sectors 216 RCUs 4356 FEC 1Gbit/s TPC Main tracking detector High particle multiplicities High data rates Complex readout electronics TPC & PHOS share a large part of the Front End Electronics Components. TPC: 216 RCUs, 4356 Front End Cards PHOS: 20 RCUs, 560 Front End Cards Based on commercial SRAM based FPGAs RCU back showing FPGAs

Readout Control Unit Readout Network Norway is responsible for Trigger handling, which is a vital part of the data readout functionality. Datapath

Trigger Busy Handling Readout Network

The Busy Box Readout Network The purpose of the Busy Box is to prevent overflow of the FEE multi event buffers. Both Firmware and Hardware has been designed by Master students in Norway. Trigger Reception Logic is shared between RCU and Busy Box. The Busy Box is currently under commisioning at CERN. To be used in several ALICE sub-detectors: TPC, PHOS, FMD, EmCAL etc.

FEE Detector Control System Control Network The purpose of the Detector Control System is to configure and monitor the Front End Electronics. Norway has responsibilities in both FEE Server and Field Layer. Field Layer includes all custom made hardware devices.

DCS board Control Network The Norwegian contribution to the DCS board is on the software and firmware side. The DCS board is used as a control node for various systems throughout ALICE. The ones that are using Norwegian firmware and, to some extent, software are: TPC, PHOS, EmCAL and FMD Readout Electronics Busy Boxes for the same experiments. Trigger OR in PHOS. Future devices like Laser DCS, Gating Grid DCS etc.

DCS Field Layer The Norwegian responsibilities in Firmware devices: Control Network The Norwegian responsibilities in Firmware devices: Phos FEC Board Controller The very low level part of DCS. FPGA that monitors the health of FEC and configures High Voltage part. RCU Xilinx FPGA. Interface towards the DCS board. RCU Auxilliary FPGA Added to increase radiation tolerance in the Xilinx FPGA by implementing Active Partial Reconfiguration. DCS board In three flavours: RCU, Busy Box and Trigger OR. The Norwegian responsibilities in Software devices: DCS board Control Engine Takes care of Low Level Communication with the registers in the FPGAs. Individual PHOS and TPC version DCS board FEE Server Encapsulates the Control Engine and implements the interface to higher layers.

RCU Radiation Tolerance Measures Control Network The dataflow will be interrupted by Single Event Upsets in the RCU Xilinx FPGA if no actions are taken. When the RCU was designed, no radiation tolerant FPGAs were available that fitted our demands. The solution is to add a small radiation tolerant control network consisting of a Actel Flash-based FPGA and a Flash Memory Device. The enables the posibility of reconfiguring the FPGA without interrupt the operation of the design. Norway is in charge of firmware and dedicated software modules. Results from irradition tests presented in next talk! DCS-board embedded computer Bank 0 Altera FPGA t Bank 1 w/ ARM cpu Bank 2 (SRAM based) Bank 3 FLASH mem w/ Linux 32 bit bus RCU motherboard Xilinx Actel Virtex-II Pro FLASH Flash Based FPGA SelectMap IF FPGA memory (SRAM based)

DCS Intercom Layer Control Network The intercom layer is a dedicated software to interface Field Layer Devices, PVSS and the Configuration Database. Current status: Fully operational both for configuration and monitoring!

PVSS Panel Example – Temperature Monitoring Control Network Screenshot from fully operational real life system!

PVSS Panel Example – Reconfiguration Status Control Network This is currently under development. The number of SEUs detected in the Xilinx is also to be used as a beam monitor.

Status FIRMWARE: PHOS Board Controller: RCU Xilinx firmware: Finalized v 3.4 Oct.2007 – Currently under testing. RCU Xilinx firmware: Trigger Receiver Module: Current version is v1.1 New version with minor revisions to meet new demands soon available. DCS interface finalized Oct 07. Aux. FPGA Firmware: Finalized 2006. Successfully tested at OCL and in the lab. Currently being tested in the real system. DCS board firmware: Final v 2.7 finished Sept 07 (to increase bandwidth of Ethernet). Earlier versions used without errors for a long time. Busy Box Firmware: Acceptance test currently ongoing. HARDWARE: Trigger OR: Finalized 2006 – currently under commisioning at CERN. Busy Box Finalized 2006. 5 new boards produced in 2007 that are currently being tested RCU, DCS and FEC (TPC/PHOS) Finalized and mass produced. (Not a Norwegian responsibility) SOFTWARE: TPC DCS network installation finished. All main components integrated (PVSS/ICL/FeeServer) Configuration and Monitoring working! Successful large scale test of monitoring performed Sept-07 with ¼ of the TPC detector

Publications and Presentations (2006 - now) NIM sec. A 2006: ”Front-End-Electronics Commication software for multiple detectors in the ALICE experiment.” Reviewed Publication in Nuclear Instruments & Methods in Physics Research, sec. A. IEEE TNS 2006: ” The control system for the front-end electronics of the ALICE time projection chamber” Reviewed publication in IEEE Transactions on Nuclear Science FPGA Forum 2006: “Case study of a solution for Active Partial Reconfiguration of a Xilinx Virtex-II pro” Conference talk. FPGA Forum 2006: ”Irradiation testing of FPGA-based readout-electronics for a large tracking detector” FPGA World 2006: ”Case study of a solution for Active Partial Reconfiguration of a Xilinx Virtex-II pro” Talk and reviewed conference proceedings. FPGA World 2007: ”Busy Generation in a Large Trigger Based Data Acquisition System” IEEE Realtime 2007: ”Radiation-tolerant, SRAM-FPGA Based Trigger and Readout Electronics for the ALICE Experiment.” Talk and conference proceedings. Reviewed publication in IEEE Transactions on Nuclear Science (accepted, to be published) THWEPP 07: ”Software environment for controlling and re-configuration of Xilinx Virtex FPGAs” Poster session and conference proceedings (to be published).

P.T. Hille, E. Olsen, T.B. Skaali, J. Wikne People J. Alme, S. Bablok, D. Fehlker, D. Larsen, M. Munkejord, M. Richter, D. Röhrich, A. Rossebø, A. Stangeland, K. Ullaland Department of Physics and Technology, University of Bergen, Norway H. Helstrup, K. Røed Faculty of Engineering, Bergen University College, Norway P.T. Hille, E. Olsen, T.B. Skaali, J. Wikne Department of Physics, University of Oslo J.I. Buskenes CERN 15