1. Peter Chochula CERN-ALICE ALICE DCS Workshop, CERN September 16, 2002 DCS – Frontend Monitoring and Control

2. Peter Chochula CERN-ALICE ALICE DCS Workshop, CERN September 16, 2002 How does DCS see the FEE ? DETECTOR FEE Private Software Supervisory Layer Well defined interface (OPC, DIM..) DCS receives user requirements: which channels have to be controlled/monitored update frequency limits relations between subsystems (e.g HV-LV) interlock requirements list of actions expected from DCS

3. Peter Chochula CERN-ALICE ALICE DCS Workshop, CERN September 16, 2002 What is the other approach? DETECTOR FEE DCS

4. Peter Chochula CERN-ALICE ALICE DCS Workshop, CERN September 16, 2002 FEE Architectures in Alice DETECTOR Control (setup of DCS Parameters…) Monitoring (Temp, I, V, Status…) DCS Supervisory Layer A/D Conversion (e.g. PLC…) Detector-DCS “Shared” architecture Detector “private” architecture Standard Software Interface DCS “private” architecture HARDWARE INTERFACE PRIVATE LINK FIELDBUSETHERNET… PRIVATE LINK FIELDBUSETHERNET…

5. Peter Chochula CERN-ALICE ALICE DCS Workshop, CERN September 16, 2002 64 channels SPD (2 drift volumes) AMBRA PASCAL 64 LV end- ladder card Interface to DCS HV end- ladder card FEE hybrid Example: SDD FEE Design LV HV DCS chip Voltage Regulators Both Control and Monitoring based on Private Interfaces

6. Peter Chochula CERN-ALICE ALICE DCS Workshop, CERN September 16, 2002 Example: SSD FEE Design (12) A128C ENDCAP Module Carrying ALABUF+ALCAPONE chips SSD Hybrid supply card JTAG monitoring of A128C JTAG control and setup of ALCAPONE LV HV (8) FEROM Crates Voltage Regulators (2) JTAG Distributors Both Control and Monitoring based on Private Interfaces

7. Peter Chochula CERN-ALICE ALICE DCS Workshop, CERN September 16, 2002 Example: TRD FEE Design Readout chamber MCM ADCs (Temp, I,V) MCM Ethernet (TCPIP) DCS ADC (Humidity, I,V) Control Workstation DCS Voltage Regulators Both Control and Monitoring based on TCP/IP Ethernet Connection

8. Peter Chochula CERN-ALICE ALICE DCS Workshop, CERN September 16, 2002 Example: HMPID FEE Design (6) FEE Segments ADC 1a ADC 1b MCM 2 MCM 1 (6) HV Segments PLC Temperature Sensors DCS (OPC) Monitoring based on Fieldbus

9. Peter Chochula CERN-ALICE ALICE DCS Workshop, CERN September 16, 2002 Example: FEE in TPC Readout Chamber FEC DCS Network Profibus (Ethernet…) RCU Both Control and Monitoring based on Fieldbus

10. Peter Chochula CERN-ALICE ALICE DCS Workshop, CERN September 16, 2002 Example: SPD FEE Design Pilot MCM SPD Alice 1

11. Peter Chochula CERN-ALICE ALICE DCS Workshop, CERN September 16, 2002 Example: SPD FEE Design Pilot MCM Analog Pilot Pixel Chip Digital Pilot GOL Laser and pin diodes SPD Alice 1 Clock Data + JTAG Out JTAG (in)

12. Peter Chochula CERN-ALICE ALICE DCS Workshop, CERN September 16, 2002 Example: SPD FEE Design Power Supplies Voltage Regulators Half Stave

13. Peter Chochula CERN-ALICE ALICE DCS Workshop, CERN September 16, 2002 Voltage Regulators Example: SDD FEE Design ROUTERROUTER ~ 200 m TTC (Trigger Timing and Control) DDL (Digital Data Link) DCS and Monitoring

14. Peter Chochula CERN-ALICE ALICE DCS Workshop, CERN September 16, 2002 DAQ Example: SPD FEE Monitoring Data Dedicated CPU (Workstation) DCS Memory DIM PVSS Halfstave control VR control JTAGJTAG Router Monitoring (Temp ) VR Control, VR Status, I,V DDL

15. Peter Chochula CERN-ALICE ALICE DCS Workshop, CERN September 16, 2002 FEE Present Configuration Model DAQ DDL CONFIG DB

16. Peter Chochula CERN-ALICE ALICE DCS Workshop, CERN September 16, 2002 DAQ SPD FEE Configuration (DDL Approach) Data Halfstave control VR control JTAGJTAG Router DDL CONFIG DB

17. Peter Chochula CERN-ALICE ALICE DCS Workshop, CERN September 16, 2002 SPD Configuration Traps: Case1 – Faulty Chip

18. Peter Chochula CERN-ALICE ALICE DCS Workshop, CERN September 16, 2002 SPD Configuration Traps: Case1 – Faulty Chip X

19. Peter Chochula CERN-ALICE ALICE DCS Workshop, CERN September 16, 2002 SPD Configuration Traps: Case1 – Faulty Chip X X

20. Peter Chochula CERN-ALICE ALICE DCS Workshop, CERN September 16, 2002 SPD Configuration Traps: Case1 – Faulty Chip X X The Instruction length has been altered! The Data and its Size have been changed !

21. Peter Chochula CERN-ALICE ALICE DCS Workshop, CERN September 16, 2002 SPD Configuration Traps: Case1 – Faulty Register

22. Peter Chochula CERN-ALICE ALICE DCS Workshop, CERN September 16, 2002 SPD Configuration Traps: Case1 – Faulty Register X

23. Peter Chochula CERN-ALICE ALICE DCS Workshop, CERN September 16, 2002 SPD Configuration Traps: Case1 – Faulty Register XX

24. Peter Chochula CERN-ALICE ALICE DCS Workshop, CERN September 16, 2002 SPD Configuration Traps: Case1 – Faulty Register XXX

25. Peter Chochula CERN-ALICE ALICE DCS Workshop, CERN September 16, 2002 SPD Configuration Traps: Case1 – Faulty Register XXXX

26. Peter Chochula CERN-ALICE ALICE DCS Workshop, CERN September 16, 2002 SPD Configuration Traps: Case1 – Faulty Register XXXX An completely altered set of instruction has been used!

27. Peter Chochula CERN-ALICE ALICE DCS Workshop, CERN September 16, 2002 SPD Operation Mode Analog Pilot Pixel Chip Digital Pilot GOL Laser and pin diodes JTAG (in) Data + JTAG Out JTAG IS INVOLVED IN ADC Monitoring Pixel chips are not accessible

28. Peter Chochula CERN-ALICE ALICE DCS Workshop, CERN September 16, 2002 SPD Configuration Mode Analog Pilot Pixel Chip Digital Pilot GOL Laser and pin diodes JTAG (in) Data + JTAG Out JTAG IS INVOLVED IN CHIP CONFIGURATION ADCs on Analog Pilot are not accessible via DCS

29. Peter Chochula CERN-ALICE ALICE DCS Workshop, CERN September 16, 2002 DAQ-DCS Synchronization with DDL involved DAQ initiates FEE setup (by sending a command) Acknowledge DAQ starts polling the status Not Ready Ready Control CPU recognizes the request Control CPU informs the DCS DAQ DDL Local Control DCS + FEE FEE Ready DCS releases the equipment and confirms the request Control CPU informs the DCS FEE Configuration

30. Peter Chochula CERN-ALICE ALICE DCS Workshop, CERN September 16, 2002 Why do we need involve ECS in configuration? It should be possible to reconfigure FEE without the presence of DAQ (recovery from power cut) DCS may need to ask for reconfiguration in some cases (e.g. voltage regulator failure)

31. Peter Chochula CERN-ALICE ALICE DCS Workshop, CERN September 16, 2002 DAQ-DCS Synchronization with DDL involved DAQ DDL Local Control DCS + FEE FEE Configuration ECS DCS DAQ DCS asks for reconfiguration of FEE ECS routes the request to DAQ Ready

32. Peter Chochula CERN-ALICE ALICE DCS Workshop, CERN September 16, 2002 DAQ-DCS Synchronization with DDL involved DAQ DDL Local Control DCS + FEE FEE Configuration ECS DCS DAQ DCS asks for reconfiguration of FEE Ready ECS routes the request to local control CPU

33. Peter Chochula CERN-ALICE ALICE DCS Workshop, CERN September 16, 2002 DAQ DAQ-DCS Synchronization with ECS involved Data Dedicated CPU (Workstation) DAQ+DCS Memory DIM DCS - PVSS Halfstave control VR control JTAGJTAG Router VR Control, VR Status, I,V CONFIG DB ECS DDL

34. Peter Chochula CERN-ALICE ALICE DCS Workshop, CERN September 16, 2002 Standard Interfaces Detectors responsibility is to provide an OPC server or DIM Server + Client along with the operation specifications In this way the choice of hardware implementation is transparent to DCS Any hardware modification will be reflected in corresponding software update

35. Peter Chochula CERN-ALICE ALICE DCS Workshop, CERN September 16, 2002 Standard Interfaces – What does it mean? Service based protocol Client can subscribe to service and define the update policy Easy to implement on different platforms Based on COM Groups and Items represent hardware Each client should be able to access any OPC server Tied to Windows platform DIM –custom protocol OPC Server OPC Group OPC Item The Real System HW0 HW1 HW2OPC Item OPC – Industrial standard Server Name Server Service Info Request Service Subscribe to service Service Data Commands Register services Client Source: C.Gaspar

36. Peter Chochula CERN-ALICE ALICE DCS Workshop, CERN September 16, 2002 Example: A VME based DCS System Local CPU MXI Physical Connection DCS

37. Peter Chochula CERN-ALICE ALICE DCS Workshop, CERN September 16, 2002 Example: A VME based DCS System Local CPU MXI Physical Connection DCS DIM Client Logical Connection DIM Server

38. Peter Chochula CERN-ALICE ALICE DCS Workshop, CERN September 16, 2002 Example: A VME based DCS System Embedded CPU Physical Connection DCS

39. Peter Chochula CERN-ALICE ALICE DCS Workshop, CERN September 16, 2002 Example: A VME based DCS System Embedded CPU Physical Connection DCS DIM Server DIM Client Logical Connection

40. Peter Chochula CERN-ALICE ALICE DCS Workshop, CERN September 16, 2002 Example: A VME based DCS System Embedded CPU Physical Connection DCS DIM Server DIM Client Logical Connection The underlying physical architecture is transparent for DCS Any modifications will appear at the level of the DIM server (the client may remain the same!)