2. Software tools for digital LLRF system integration at CERN 04/11/2015 LLRF15, Software tools2 Andy Butterworth Tom Levens, Andrey Pashnin, Anthony Rey

3. Outline Digital LLRF and control system overview Consistency between firmware & software Tools for memory map management Extensions to help productivity Future plans & conclusions 04/11/2015 LLRF15, Software tools3

4. Digital LLRF at CERN LINAC 4 ELENA Digital LLRF systems in 8 machines + more coming soon ~75 types of VME module (distinct firmware)

5. Seen by the LLRF designer: 04/11/2015 LLRF15, Software tools5

6. Seen by the LLRF designer: VME bus 04/11/2015 LLRF15, Software tools6 Memory map VHDL memory map

7. LabVIEW, Python… Linux Front End Computer (FEC) Server task Seen by the software developer: VME board Device driver Device access library Real-time task Data store VME board CMW server API VME bus CMW C++ client API LSA/InCA, MATLAB… CMW Java client API Driver (generated by Encore tool) FESA class (generated + device-specific user code) Controls MiddleWare (CMW) 04/11/2015 LLRF15, Software tools7 Device/property interface

8. Linux device drivers (the old way) Hardware Database Device driver Device access library Encore Driver generation tool Entered by hand libmy_device.a libmy_device.h Must match driver and HW Compilation of FESA class 04/11/2015 LLRF15, Software tools8 Excel file

9. FESA class Mismatches possible Device driver Device access library VME board VME bus Mismatch between firmware and driver: Error in Excel file or while manually entering memory map in database Flashed new firmware, forgot to redeliver driver and rebuild software Mismatch between compiled user code and driver: Error in deploying driver Installed new driver, FESA class not correctly redelivered Both cases result in access to wrong registers and unpredictable behaviour 04/11/2015 LLRF15, Software tools9

10. Solution Master memory map description in XML file Generate driver configuration file and VHDL from same master file 04/11/2015 LLRF15, Software tools10 my_device.xml driver configuration VHDL memory map libmy_device.a libmy_device.h FPGA firmware Keep driver, software and firmware in sync

11. Memory map editor 04/11/2015 LLRF15, Software tools11 Edit register and memory map Automatic address calculation and alignment Enter attributes: name, size, width, read/write… Validate Generate VHDL Generate driver

12. Documentation Web pages Web documentation generated from XML via XSLT 04/11/2015 LLRF15, Software tools12

13. Register block reuse Certain register blocks occur in many designs acquisition memories, function generators… Can be saved as sub-maps in separate XML files and included in memory map C++ libraries written for complex functionalities e.g. acquisition memory buffers 04/11/2015 LLRF15, Software tools13

14. Sub-maps 04/11/2015 LLRF15, Software tools14 Submap

15. FESA class generation HW designers: want access to every functionality of the board (whole register map) want it yesterday reserve the right to change the register map whenever they want Lots of tedious coding in FESA C++ We have the memory map description; why not generate the FESA code as well? 04/11/2015 LLRF15, Software tools15

16. FESA class generation Generate design file and C++ source for FESA class Meant for testing: exposes registers as FESA device properties 04/11/2015 LLRF15, Software tools16 my_device.xml driver configuration libmy_device.a libmy_device.h FESA class design file & C++ source FESA class for testing

17. FESA class generation Simple access to registers is not enough Need to know the semantics of the register numeric type or bit field composed of sub-registers? conversion factors/algorithms 04/11/2015 LLRF15, Software tools17

18. Register semantics 04/11/2015 LLRF15, Software tools18 Bit-field Sub-registers

19. Register semantics 04/11/2015 LLRF15, Software tools19 Code-field (enum)

20. Other FESA class functionality Many additional features added to support FESA class functionality: Virtual registers: only exist in FESA class Alarm generation for fault bits Multiplexed data store and real-time code for multi-cycling machines … 04/11/2015 LLRF15, Software tools20 Allows to have a fully working FESA class generated automatically (for commissioning purposes). Represents a substantial time saving for SW developers.

21. Further HDL generation A companion tool (Gena) can be launched to generate the full VHDL register block 04/11/2015 LLRF15, Software tools21 The main tool (Cheburashka) generates only the VHDL memory map

22. Gena Python script which reads master XML memory map file Produces VHDL code for the entire register control block Supports all standard register types (R/W/RW/RMW). Registers are auto-split into bits/sub-registers if these are defined. Supports multiple memories, each with own data and strobe inputs. Supports multiple “areas” of registers, each gets its own multiplexer set. 04/11/2015 LLRF15, Software tools22 T. Levens Generates large amount of FW previously done by hand. Represents a substantial time saving for FW developers.

23. Next steps Looking at re-implementation of FESA code generation in Python using Jinja2 template package Cheburashka is currently implemented as a Java application Continual enhancement (feature creep) has caused it to become very large and complex Better encapsulation of functionality (library) Generation of Python package for test scripts Replace GUI with generic XML editor? 04/11/2015 LLRF15, Software tools23

24. Summary Tools for consistent memory map management developed in the RF group Automated generation of VHDL and C++ code avoids a lot of tedious coding In production since 2013 in the RF and Beam Instrumentation groups Used by all LLRF designers and SW developers for all new developments in the RF group 04/11/2015 LLRF15, Software tools24

25. Thank you for your attention! 04/11/2015 LLRF15, Software tools25