Modified Harvard Architectures

Introduction to Atmel AVR The AVR architecture was conceived by two students at the Norwegian Institute of Technology (NTH) Alf-Egil Bogen and Vegard Wollan. The AVR is a modified Harvard architecture 8-bit RISC single chip microcontroller which was developed by Atmel in 1996. The AVR was one of the first microcontroller families to use on-chip flash memory for program storage, as opposed to one-time programmable ROM, EPROM, or EEPROM used by other microcontrollers at the time. The AVR is a modified Harvard architecture machine where program and data is stored in separate physical memory systems that appear in different address spaces, but having the ability to read data items from program memory using special instructions. "

Harvard Architecture Howard Hathaway Aiken The Harvard architecture is a computer architecture with physically separate storage and signal pathways for instructions and data. The term originated from the Harvard Mark I relay-based computer, which stored instructions on punched tape (24 bits wide) and data in electro-mechanical counters. In a Harvard architecture, there is no need to make the two memories share characteristics. In particular, the word width, timing, implementation technology, and memory address structure can differ. In some systems, instructions can be stored in read-only memory while data memory generally requires read-write memory. In some systems, there is much more instruction memory than data memory so instruction addresses are wider than data addresses.

Von Neumann Architecture John von Neumann In contrast with the Harvard architecture, the Von Neumann architecture has a single storage structure to hold both instructions and data. The CPU can be either reading an instruction or reading/writing data from/to the memory because instructions and data use the same bus system. The phrase Von Neumann architecture derives name of the mathematician and early computer scientist John von Neumann. The meaning of the phrase has evolved to mean a stored-program computer in which an instruction fetch and a data operation cannot occur at the same time because they share a common bus. This is referred to as the Von Neumann bottleneck and often limits the performance of the system.

Modified Harvard Architecture A modified Harvard architecture machine is very much like a Harvard architecture machine, but it relaxes the strict separation between instruction and data while still letting the CPU concurrently access two (or more) memory buses. The most common modification includes: Separate instruction and data caches backed by acommon address space. While the CPU executes from cache, it acts as a pure Harvard machine. When accessing backing memory, it acts like a von Neumann machine (where code can be moved around like data, a powerful technique). This modification is widespread in modern processors such as the ARM architecture and X86 processors. Provides a pathway between the instruction memory (such as ROM or flash) and the CPU to allow words from the instruction memory to be treated as read-only data. This technique is used in some microcontrollers, including the Atmel AVR. This allows constant data, such as text strings or function tables, to be accessed without first having to be copied into data memory, preserving scarce (and power-hungry) data memory for read/write variables. Special machine language instructions are provided to read data from the instruction memory. (This is distinct from instructions which themselves embed constant data, although for individual constants the two mechanisms can substitute for each other.)

Processor ISA: RISC versus CISC Emphasis on hardware Emphasis on software Include multi-clock complex instructions Include single-clock reduce instruction only Memory-to-memory: “Load” and “Store” incorporated in instructions Register-to-register: “Load” and “Store” are independent instructions Small code sizes, high cycles per second Low cycles per second, large code sizes Transistors used for storing complex instructions Spends more transistors on memory registers RISC vs. CISC is a topic quite popular on the Net. Every time Intel (CISC) or Apple (RISC) introduces a new CPU, the topic pops up again. Most PC's use CPU based on CISC architecture. For instance Intel and AMD CPU's are based on CISC architectures. Many claim that RICS is the architecture of the future. But even though RISC has been in the market since 1980, it hasn’t managed to kick CISC out of the picture, some argue that if it is really the architecture of the future it should have been able to do this by now.

ATMega32 Pin out & Descriptions Clears all the registers and restart the execution of program Provides supply voltage to the chip. It should be connected to +5 Port B Port A Reference voltage for ADC These pins are used to connect external crystal or RC oscillator Supply voltage for ADC and portA. Connect it to VCC Port C Port D

ATMega32 Pin out & Descriptions

ATMega32 Pin out & Descriptions

ATMega32 Pin out & Descriptions Digital IO is the most fundamental mode of connecting a MCU to external world. The interface is done using what is called a PORT. A port is the point where internal data from MCU chip comes out or external data goes in. They are present is form of PINs of the IC. Most of the PINs are dedicated to this function and other pins are used for power supply, clock source etc . ATMega32 ports are named PORTA, PORTB, PORTC, and PORTD.