1. PROGRAMMABLE LOGIC CONTROLLERS SINGLE CHIP COMPUTER
SINGLE CHIP COMPUTER (SCC) REFERS TO ONE SINGLE IC CHIP THAT HAS ALL THE COMPONENTS OF A COMPUTER

2. PROGRAMMABLE LOGIC CONTROLLERS SINGLE CHIP COMPUTER
USUALLY A SCC CHIP CONTAINS CPU, MEMORY AND I/O

3. PROGRAMMABLE LOGIC CONTROLLERS SINGLE BOARD COMPUTER
SINGLE BOARD COMPUTER (SBC) REFERS TO A COMPUTER MADE UP BY DISCRETE COMPONENTS ON A SINGLE BOARD

4. PROGRAMMABLE LOGIC CONTROLLERS SINGLE BOARD COMPUTER
IT USUALLY CONTAINS ON BOARD CPU, MEMORY AND I/O

5. PROGRAMMABLE LOGIC CONTROLLERS SINGLE BOARD COMPUTER
MODERN PERSONAL COMPUTERS ARE USUALLY SINGLE BOARD COMPUTERS

6. PROGRAMMABLE LOGIC CONTROLLERS RISC VERSUS CISC
RISC (REDUCED INSTRUCTION SET COMPUTER) IS A NEWER INVENTION THAN THE TRADITIONAL CISC (COMPLEX INSTRUCTION SET COMPUTER)

7. PROGRAMMABLE LOGIC CONTROLLERS RISC VERSUS CISC
RISC CONTAINS ONLY A FEW BASIC INSTRUCTIONS, ALL COMPLEX INSTRUCTIONS ARE DERIVED FROM THESE SIMPLE INSTRUCTIONS

8. PROGRAMMABLE LOGIC CONTROLLERS RISC VERSUS CISC
RISC IS MORE EFFICIENT BECAUSE IT REQUIRES LESS CYCLE FOR EACH INSTRUCTION

9. PROGRAMMABLE LOGIC CONTROLLERS RISC VERSUS CISC
RISC IS MOSTLY USED CURRENTLY IN PORTABLE AND EMBEDDED APPLICATIONS

10. PROGRAMMABLE LOGIC CONTROLLERS RISC VERSUS CISC
CISC CONTAINS MANY COMPLEX INSTRUCTIONS

11. PROGRAMMABLE LOGIC CONTROLLERS RISC VERSUS CISC
EXAMPLE: INSERT AN ELEMENT INTO A DOUBLE-LINKED LIST

12. PROGRAMMABLE LOGIC CONTROLLERS RISC VERSUS CISC
CISC REQUIRES MORE ADVANCED FEATURES SUCH AS PIPELINING IN ORDER TO HANDLE THESE INSTRUCTIONS

13. PROGRAMMABLE LOGIC CONTROLLERS MACHINE LANGUAGE
IT IS GENERALLY WRITTEN IN BINARY

14. PROGRAMMABLE LOGIC CONTROLLERS MACHINE LANGUAGE
THIS BINARY IS ALSO AN EXPRESSION OF THE INPUTS TO THE ARITHMETIC LOGIC UNIT

15. PROGRAMMABLE LOGIC CONTROLLERS MACHINE LANGUAGE
MACHINE LANGUAGE IS VERY CPU SPECIFIC
EACH CPU HAS ITS OWN INSTRUCTIONS

16. PROGRAMMABLE LOGIC CONTROLLERS WHAT DO ALL THE INSTRUCTIONS GO?
MANY PEOPLE SAY COMPUTER CAN UNDERSTAND MACHINE CODE

17. PROGRAMMABLE LOGIC CONTROLLERS WHERE DO ALL THE INSTRUCTIONS GO?
A COMPUTER PHYSICALLY EXECUTES THESE COMMANDS AS A PROGRAMMABLE LOGIC CONTROLLER

18. PROGRAMMABLE LOGIC CONTROLLERS WHAT DO ALL THE INSTRUCTIONS GO?
HERE IS A SIMPLE FLOW CHART

19. PROGRAMMABLE LOGIC CONTROLLERS MEMORY
MEMORY IS WHERE ALL THE INSTRUCTIONS GO

20. PROGRAMMABLE LOGIC CONTROLLERS MEMORY
DATA BUS FROM THE MEMORY GOES INTO CPU DATA BUS FOR INSTRUCTION / DATA TRANSFER

21. PROGRAMMABLE LOGIC CONTROLLERS MEMORY
PROGRAMMABLE LOGIC CONTROLLERS MEMORY
ADDRESS BUS IS CONNECTED TO AN ADDRESS DECODER (USUALLY A COUNTER) THAT INCREASES EVERY CLOCK CYCLE

22. PROGRAMMABLE LOGIC CONTROLLERS MEMORY
CLOCK IS GENERATED BY A FREE RUNNING OSCILLATOR WHICH ALSO DETERMINES HOW FAST CAN INSTRUCTIONS FLOW INTO THE CPU

23. PROGRAMMABLE LOGIC CONTROLLERS MEMORY
CONTROL BUS IS TO CONTROL SIGNALS GENERATED BY THE CPU

27. PROGRAMMABLE LOGIC CONTROLLERS ASSEMBLY
ASSEMBLY LANGUAGE INTRODUCES THE WORD MNEMONICS
LDA = LOAD INTO REGISTER A

28. PROGRAMMABLE LOGIC CONTROLLERS ASSEMBLY
A WORD IS USED TO REPRESENT BINARY OPERATORS
EX: “MOV” INSTEAD OF “0x07”

29. PROGRAMMABLE LOGIC CONTROLLERS ASSEMBLY
ASSEMBLY LANGUAGE IS CPU SPECIFIC DUE TO ITS DIRECT TRANSLATION

30. PROGRAMMABLE LOGIC CONTROLLERS HIGHER LEVEL LANGUAGES & COMPILATION
AS PROGRAMS GET MORE COMPLICATED, COMPILERS WERE DEVELOPED

31. PROGRAMMABLE LOGIC CONTROLLERS HIGHER LEVEL LANGUAGES & COMPILATION
COMPILIERS RESULT IN HIGH LEVEL LANGUAGES
“C” IS A TYPICAL LANGUAGE THAT REQUIRES COMPILATION

32. PROGRAMMABLE LOGIC CONTROLLERS HIGHER LEVEL LANGUAGES & COMPILATION
“C” IS MORE CPU INDEPENDENT THAN ASSEMBLY BECAUSE DIFFERENT COMPILERS GENERATED MACHINE LANGAUGES FOR EACH CPU

33. PROGRAMMABLE LOGIC CONTROLLERS CLOSER LOOK AT A COMPILER
LEXICAL ANALAYSIS: FIRST STAGE
THE PURPOSE OF LEXICAL ANALYZERS IS TO TAKE A STREAM OF INPUT CHARACTERS AND DECODE THEM INTO A HIGHER LEVEL

34. PROGRAMMABLE LOGIC CONTROLLERS CLOSER LOOK AT A COMPILER
SYNTACTIC ANALAYSIS: SECOND STAGE
TAKES THE PROGRAM SOURCE CODE AND ENSURES THE PROGRAM'S SYNTACTICAL CORRECTNESS AND BY BUILDING AN INTERNAL REPRESENTATION OF THE PROGRAM

35. PROGRAMMABLE LOGIC CONTROLLERS CLOSER LOOK AT A COMPILER
CODE GENERATION: THIRD STAGE
THE OBJECTIVE CODE IS GENERATED (MACHINE CODE WITHOUT EXTERNALS AND STATIC LIBRARIES LINKED)

36. PROGRAMMABLE LOGIC CONTROLLERS EXAMPLE CPU: PIC16F84
PIC16F84 IS A LOW-END 8-BIT MICROCONTROLLER (SCC) MANUFACTURED BY MICROCHIP

37. PROGRAMMABLE LOGIC CONTROLLERS EXAMPLE CPU: PIC16F84
MAXIMUM FOR THIS MICROCONTROLLER IS 10 MHZ BUT WE USUALLY CLOCK IT AT 4 MHZ

38. PROGRAMMABLE LOGIC CONTROLLERS EXAMPLE CPU: PIC16F84
THIS MICROCONTROLLER HAS A BUILT-IN CRYSTAL DRIVER, DATA RAM, FLASH PROGRAM MEMORY, TTL BUFFERED I/O AND MANY SPECIAL FUNCTION REGISTERS

40. PROGRAMMABLE LOGIC CONTROLLERS EXAMPLE CPU: ARCHITECTURE OVERVIEW
INPUT CLOCK IS DIVIDED INTO Q1, Q2, Q3 AND Q4. IN Q1 CYCLE, INSTRUCTION IS FETCHED FROM THE PROGRAM MEMORY THROUGH INSTRUCTION REGISTER

41. PROGRAMMABLE LOGIC CONTROLLERS EXAMPLE CPU: ARCHITECTURE OVERVIEW
INPUT CLOCK IS DIVIDED INTO Q1, Q2, Q3 AND Q4. IN Q2 CYCLE, INSTRUCTION IS SEPARATED INTO OP-CODE AND OP-RAND. OP-CODE GOES INTO THE INSTRUCTION DECODER. OP-RAND GOES TO ALU

42. PROGRAMMABLE LOGIC CONTROLLERS EXAMPLE CPU: ARCHITECTURE OVERVIEW
INPUT CLOCK IS DIVIDED INTO Q1, Q2, Q3 AND Q4. IN Q3 CYCLE, OP-RAND AND DATA FROM DATA RAM OR W REGISTER (WORKING REGISTER) ARE PUT INTO ALU.

43. PROGRAMMABLE LOGIC CONTROLLERS EXAMPLE CPU: ARCHITECTURE OVERVIEW
INPUT CLOCK IS DIVIDED INTO Q1, Q2, Q3 AND Q4. IN Q4 CYCLE, RESULT IS PUT INTO THE W REGISTER.

44. PROGRAMMABLE LOGIC CONTROLLERS EXAMPLE CPU: HARDWARE CONNECTIONS
PIC16F84 HAS 18 PINS. FROM TOP LEFT THEY ARE RA2, RA3, RA4, MCLR, VSS, RB0, RB1, RB2, RB3, RB4, RB5, RB6, RB7, VDD, OSC2, OSC1, RA0, RA1

45. PROGRAMMABLE LOGIC CONTROLLERS EXAMPLE CPU: HARDWARE CONNECTIONS
RA0 – RA4 AND RB0 – RB7 ARE GENERAL I/O PORTS. RB0 CAN ALSO BE USED AS EXTERNAL INTERRUPT INPUT

46. PROGRAMMABLE LOGIC CONTROLLERS EXAMPLE CPU: HARDWARE CONNECTIONS
MCLR IS AN ACTIVE LOW RESET INPUT. IT IS SET LOGIC HIGH DURING NORMAL OPERATION, AND PULLED LOW TO RESET THE CPU

47. PROGRAMMABLE LOGIC CONTROLLERS EXAMPLE CPU: HARDWARE CONNECTIONS
VSS IS GROUND CONNECTION AND VDD IS SUPPLY VOLTAGE CONNECTION

48. PROGRAMMABLE LOGIC CONTROLLERS EXAMPLE CPU: HARDWARE CONNECTIONS
OSC1 CONNECTS TO ONE PIN OF THE CRYSTAL AND OSC2 CONNECTS TO ANOTHER PIN OF THE CRYSTAL