Optical data transmission for the ATLAS phase-I upgrade trigger electronics S. Hou Academia Sinica O7 台達館 R107 2015/01/30 13:00

LHC upgrade timeline 2009 Run 1 Start of LHC √s =7, 8 TeV, ∫ L= 25 fb-1 2013/14 machine consolidation LS1 √ s = 13, 14 TeV, expecting ∫ L ~75 fb-1 2018 Phase- I upgrade LS2 √ s = 13, 14 TeV, expecting ∫ L ~300 fb-1

Challenges to ATLAS Phase-I upgrade TRIGGER RATE OVERBOUND Event pileup up to 80 per bunch crossing  keep trigger threshold around 20-25 GeV muon pT thresholds not effective in the forward region higher EM ET thresholds in physics acceptance  Improve trigger efficiency all upgrades to be compatible with Phase-II  New Muon Small Wheels for forward trigger and tracking  high granularity calorimeter Level-1 trigger  Fast track trigger (Pixel + SCT)  Forward physics system

Muon Spectrometer New Small Wheel pT measurement : Monitored Drift Tube (MDT) Cathode Strip Chamber (CSC) Barrel Trigger : Resistive Plate Chambers (RPC) Endcatp Trigger: Thin Gap Chambers (TGC) New Small Wheel multilayer chambers kill fake triggers at Level-1 by IP pointing δθ ~ 1 mrad  a trigger rate reduction ~6 Phase-0  Phase-I

New Small Wheel upgrade 16 sectors per wheel, each sector has 2x4 sTGC (Thin Gap Chambers) layers 2x4 MM (MicroMegas) layers sTGC MicroMegas

New Small Wheel trigger upgrade Add NSW sTGC trigger  muon track δθ < 1 mrad reduce noise tracks ATLAS trigger limits L1 : ~75 kHz max L2 : ~3.5 kHz max EF : ~200 Hz max (kHz) Forward muon trigger at L= 3×1034 MU11 events selected analysis Upgrade L1 with NSW

NSW trigger, data flow sTGC latency budget: 1025 ns min max (ns)

NSW sTGC trigger circuits

NSW sTGC trigger Router Repeater to clean and amplify signals from TDS: 4.8 Gbps FPGA selects active TDS signals to transmit Optical transmitter over 100 m fiber to trigger hub: >4.8 Gbps Routing by Switching, optimize occupancy TDS inputs assigned to possible fiber outputs Choose active TDS lines to fibers Challenges: Custom Radhard AISC: IBM 130nm Rad-hard of all components Routing FPGA latency <100 ns Rad-hard optical transmitter 4.8 Gbps copper wires over 5 m

sTGC Router Firmware Router Processing Unit Basic GTP RX logic + Syn. Buffer Cut-Through Switching Flexible 16 to 3 Router Algorithm Recovery of 16 Ch x 120 bit input & 16 Ch x 1bit flag Any 3 “hit” at the same time (e.g. Fig.1 Ch-6, Ch-11 and Ch-14) 3Ch x 120 bit data output Optimized GTP TX logic

sTGC Router Latency evaluation

sTGC Router prototype prototype V0 using Artix-7 FPGA Route prototype V0 Dec 2014 prototype V0 using Artix-7 FPGA for evaluation of design, production quality data link speed capacity Radiation hardness

sTGC Router prototype tests Router prototype V0 tests functional tests of component: power chips, FGPA Twinnax copper wire loop tests: 4.8 Gbps FGPA tests: Logic, Bit-Error-Rate, bank I/O MGTX1Y1 & MGTX1Y3: SFP Link MGTX1Y5 & MGTX1Y6 & MGTX1Y67: SMA Twinax Link

Router optical transmitter Two choices only for phase I : VTTx or MTx  limited by Rad-hard drivers (GBLD 4.8 Gbps, LOCld 8 Gbps)  same function, MTx has faster driver MTx production and QA:  MTx is customized for ATLAS Lar space limits joint-development of SMU+AS .. ATLAS Phase-I quantities: LAr 2500, NSW 400 modules being evaluated for production in Taiwan (by Liverage)

ATLAS MTx Optical transmitter 1. use VCSEL in TOSA package, 850 nm, MM, 10 GHz 2. LOCld drivers 3. customized connector fiber latch to fit in LAr space requirement

MTx transmitter prototyping 1. evaluation of Truelight TOSA, 85/85 burn, radiation hardness 2. prototype module production using Onet 8501 driver (by Liverage, dec 2014) MTX-Onet module Test fanout board, SMA to I/O e.g. Kintex7, Scope typical 10 Gbps eye diagram

Summary ATLAS Phase-I New Small Wheel  is approval, TDR ready, MoU in early 2014  to be constructed by 2107 Development for NSW sTGC Router  Prototyping is successful for Router, Optical transmitter  Proceeds to functionality and Radhard tests