Reconfigurable Computing - VHDL - Types John Morris Chung-Ang University The University of Auckland

Types VHDL is a fully-fledged programming language with a rich type system* Types include Those normally found in high level programming languages integer, character, real, … Example declarations VARIABLE a, b : integer := 0; x, y : real := 1.2e-06; p : character; You can give a variable an initial value when you declare it! *Computer scientist’s jargon for “You can make all the data types you need”

Types - Defining precision and range Sub-types Ada (and therefore VHDL) has a very flexible means of specifying exactly the requirements for representations (physical realizations) of numbers This capability is important for efficient physical realizations If you write VARIABLE x : integer; in your model, the synthesizer has to `guess’ how many bits of precision that you need for x! However, if you write VARIABLE x : integer RANGE 0 .. 255; then the compiler knows that an 8-bit representation will be adequate! Specifying the range of a data type is essential for efficient implementation You don’t want the synthesizer to generate a 32-bit adder/subtracter/multiplier/… when an 8-bit one would do!

Literals – or constants Most literals are similar to other languages Integers – 0, 1, +1, -5, … Reals – 0.0, 3.24, 1.0e+6, -6.5e-20, … Characters – ‘A’, ‘a’, ‘(’, … Strings (formally arrays of characters) – “clockA”, “data”, … For efficient digital circuit modeling, We need to specify numbers in binary, octal, hexadecimal Ada and VHDL use a form: base#number# Examples: 2#001110#, 8#76771#, 16#a5a5#

Additional standard types Boolean Values are ‘true’ and ‘false’ VARIABLE open, on : boolean := false; Natural The natural numbers from 0 → n n is implementation defined Commonly n = 232-1 Positive Numbers from 1 → n Good practice tip! Use boolean, natural and positive when appropriate eg for counters use natural rather than integer This helps the simulator detect errors in your program!

Libraries VHDL’s standard defines a number of libraries or ‘package’s (using the Ada term) The most useful is the IEEE 1164 standard logic package To use it, add to the start of your program: This library is just a VHDL package You can usually find the source of it on your system It is worthwhile looking through it … it provides many useful examples of VHDL capabilities! LIBRARY ieee; USE ieee.std_logic_1164.all;

IEEE 1164 standard logic package std_logic is the most important type in this package It’s an enumerated type: TYPE std_logic IS (‘U’, ‘X’, ‘0’, ‘1’, ‘Z’, ‘W’, ‘H’, ‘L’, ‘-’ ); ‘U’ Unknown ‘X’ Forcing unknown ‘0’ Forcing 0 ‘1’ Forcing 1 ‘Z’ High impedance ‘W’ Weak unknown ‘L’ Weak 0 ‘H’ Weak 1 ‘-’ Don’t care

IEEE 1164 standard logic package You should always use std_logic in place of the (apparently) simpler bit type! bit has values (‘0’, ‘1’) only Always use the simplest possible type? Not in this case!! ‘Digital’ circuits are really analogue circuits in which we hope we can consider 0 and 1 values only! Use of std_logic allows the simulator to pinpoint sources of error for you!

IEEE 1164 standard logic package std_logic lets the simulator pinpoint errors for you! ‘U’ – indicates a signal which has not yet been driven A good design will ensure all signals are in known states at all times A probable source of error in a properly designed circuit ‘X’ → two drivers are driving a signal with ‘0’ and ‘1’ A definite error! Good design practice would ensure All signals are defined in a reset phase No ‘U’’s appear in the simulator Lines are never driven in opposite directions Can cause destruction of drivers and catastrophic failure High power consumption Examine simulator traces for ‘X’ – there shouldn’t be any!

IEEE 1164 standard logic package Bus pull-up and pull-down resistors can be ‘inserted’ Initialise a bus signal to ‘H’ or ‘L’: ‘0’ or ‘1’ from any driver will override the weak ‘H’ or ‘L’: SIGNAL not_ready : std_logic := ‘H’; VDD 10k /ready DeviceA DeviceB DeviceC IF seek_finished = ‘1’ THEN not_ready <= ‘0’; END IF;

IEEE 1164 standard logic package Bus drivers can be disconnected After a bus signal has been driven, it’s necessary to ‘release’ it: eg once this device has driven not_ready, it should release it so that another device on the bus can assert (drive) it SIGNAL not_ready : std_logic := ‘H’; IF seek_finished = ‘1’ THEN not_ready <= ‘0’; END IF; … -- Perform device actions -- Now release not_ready not_ready <= ‘Z’;

Standard logic buses VHDL supports arrays Define an array with In digital logic design, arrays of std_logic are very common, so a standard type is defined: std_logic_vector is defined as an unconstrained array: This means that you can supply the array bounds when you declare the array: TYPE bus8 IS ARRAY(0 to 7) OF std_logic; data: bus8 := “ZZZZZZZZ”; data: std_logic_vector(0 to 7) := “ZZZZZZZZ”; TYPE std_logic_vector IS ARRAY(integer RANGE <>) OF std_logic; We will learn more about unconstrained arrays later. Using them allows you to make complex models which you can use in many situations! cmd: std_logic_vector(0 to 2) := “010”; address: std_logic_vector(0 to 31);

Attributes Attributes of variables and types are the values of properties of types and variables Define an array with In digital logic design, arrays of std_logic are very common, so a standard type is defined: std_logic_vector is defined as an unconstrained array: This means that you can supply the array bounds when you declare the array: TYPE bus8 IS ARRAY(0 to 7) OF std_logic; data: bus8 := “ZZZZZZZZ”; data: std_logic_vector(0 to 7) := “ZZZZZZZZ”; TYPE std_logic_vector IS ARRAY(integer RANGE <>) OF std_logic; We will learn more about unconstrained arrays later. Using them allows you to make complex models which you can use in many situations! cmd: std_logic_vector(0 to 2) := “010”; address: std_logic_vector(0 to 31);

Architectures – Architectural style Exercise Complete the structural model for a full adder by adding the `circuitry’ for the carry out signal Write a (very short) paragraph describing how your additions to the full adder model work. If you do this, I will also try to help you improve your technical English by carefully correcting your paragraph. (Hopefully, if we start with some short, simple exercises, you will become much more fluent before the end of semester!) Bring your exercise to the lecture on Tuesday morning.