1. EGR 2131 Unit 8 VHDL for Combinational Circuits
Read Brown & Vranesic, Sections 6.6 to 6.8 and Sections A.7 to A.9.
Homework #8 and Lab #8 due next week.
Quiz next week.
-Handouts: Quiz, Unit 8 Practice sheets.

2. Different Numeric Codes
Before our main topic, we’ll look briefly at Gray code and at a converter circuit that works with this code.
Different codes exist for using 1s and 0s to represent positive integers.
Standard binary code
Example: In standard binary, 15 is 1111.
Binary-coded decimal (BCD)
Example: In BCD, 15 is
Gray code
Example: In Gray code, 15 is 1000.
Gray code was briefly mentioned in Chapter 4 w.r.t. K-maps, and appears again in the book’s Example 6.28 (p. 367).

3. Four-Bit Gray Code
The key feature of Gray code is that only one bit changes when we increase a number by one.
This is not true of standard binary.

4. Why is Gray Code Useful?
Gray code is used for rotary encoders that sense the angular position of a shaft or axle.
From Wikipedia article on rotary encoders:
-Do Practice Questions 1, 2, 3, 4.
Standard 3-bit binary code: no good!
3-bit Gray code: better!

5. Review: Code Converters
If a digital system needs to handle numbers using two different codes, it needs circuitry to convert between the two codes.
Examples of code converters:
74184 BCD-to-binary and binary-to-BCD converter
Binary-to-Gray code or Gray-code-to-binary converters (see next slide)

6. Textbook Example 6.28: Design a 3-Bit Binary to Gray Code Converter
-Do Practice Question 5. A homework problem will have them design a converter in the other direction.
Equations from
truth table
Truth table
Circuit
The pattern seen here in the equations and circuit extends to an arbitrary number of bits.

7. VHDL Selected Signal Assignment Statement
The general form of a selected signal assignment statement is:
WITH expression SELECT
signal_name <= signal_value WHEN constant,
{signal_value WHEN constant,}
[signal_value WHEN OTHERS];
The braces indicate optional content that that may appear as many times as desired.
When the statement is executed, if the optional OTHERS clause is omitted, one and only one of the constants must match the value of expression; the corresponding signal_value is then assigned to the signal named on the left.
If the OTHERS clause is present, the signal_value associated with OTHERS is used if none of the preceding constants match.

8. VHDL Selected Signal Assignment Statement: Example #1
For this example, assume that signals w0, w1, and sel have mode IN and type STD_LOGIC; and assume that signal y has mode OUT and type STD_LOGIC.
WITH sel SELECT
y <= w0 WHEN '0',
w1 WHEN OTHERS;
What does this code do? It’s a 2-to-1 MUX.
Do Practice Question 6.

9. Selected Signal Assignment Statement: Example #2
Selected signal assignments make it easy to code truth tables directly in VHDL code.
For this example, assume that signal x has mode IN and type STD_LOGIC_VECTOR(1 TO 3); and assume that signal f has mode OUT and type STD_LOGIC.
WITH x SELECT
f <= '1' WHEN "001",
'1' WHEN "011",
'1' WHEN "100",
'0' WHEN OTHERS;
Do as Practice Question 7.

10. VHDL Conditional Signal Assignment Statement
The general form of a conditional signal assignment statement is:
signal_name <= expression WHEN logic-expression [ELSE]
{expression WHEN logic-expression [ELSE]}
[expression];
When the statement is executed, the logic_expressions are evaluated in order until a true one is found; the corresponding expression is then evaluated and the resulting value is assigned to the signal named on the left. If none of the logic-expressions are true, the last expression (if present) is used.
-Note that the reserved word WHEN appears in both the selected signal assignment and the conditional signal assignment.
-Don’t confuse the assignment operator <= with the comparison operator <=.
Each logic-expression typically consists of signal names or constants combined with comparison operators =, /=, <, <=, >, >=.

11. VHDL Conditional Signal Assignment Statement: Example #1
For this example, assume that signals w0, w1, and sel have mode IN and type STD_LOGIC; and assume that signal y has mode OUT and type STD_LOGIC.
y <= w0 WHEN sel = '0' ELSE
w1;
What does this code do? It’s another way to implement a 2-to-1 MUX.
Do Practice Question 8.

12. VHDL Conditional Signal Assignment Statement: Example #2
For this example, assume that signals x1, x2, and x3 have mode IN and type STD_LOGIC; and assume that signal f has mode OUT and type STD_LOGIC.
f <= x1 WHEN x2 = '1' ELSE
NOT x1 WHEN x2 = '0' AND x3 = '0' ELSE
x3 WHEN x1 = '1' ELSE
'0';
Do as Practice Question 9. (x87)
-Note that it works top-down so you can’t just say that x<=c whenever a=1.

13. Which One Should I Use: Selected or Conditional?
Selected assignment statements and conditional assignment statements are similar to each other, and in many cases you could use either one.
But there are differences, and with experience you’ll come to recognize cases where one type is preferable over the other.
For example, selected assignment statements must cover every possible case, but conditional assignment statements need not do so….

14. Which One Should I Use: Selected or Conditional? (Cont’d.)
Recall the general form of a selected assignment:
The cases listed here must cover every possible value of expression.
Therefore, the following statement is illegal, since it does not cover the case where sel = WITH sel SELECT
y <= w0 WHEN '0';

15. Which One Should I Use: Selected or Conditional? (Cont’d.)
Now recall general form of a conditional assignment:
The cases listed here need not cover every possible case.
Therefore, the following statement is legal, even though it doesn’t cover the case where sel = y <= w0 WHEN sel = '0';

16. Review from Unit 6: Hierarchical Approach in VHDL Code
Recall that one style of VHDL coding uses a hierarchical approach that builds up a complex circuit (such as a 4-bit adder) from a simple component (such as a full adder).
A COMPONENT declaration may be located within the ARCHITECTURE (as here) or in a separate PACKAGE.
Each of these statements instantiates a copy of the component described in the COMPONENT declaration above.

17. Review From Unit 7: Bigger MUXes Built from Smaller MUXes
Recall also that we can build a 16-to-1 MUX using several 4-to-1 MUXes.
Looks like a perfect opportunity to use the hierarchical approach that we just reviewed.

18. VHDL Code for Making a 16-to-1 MUX from 4-to-1 MUXes
Here is complete code for a 4-to-1 MUX, using a selected signal assignment. (Could use conditional signal assignment instead.) 18

19. VHDL Code for Making a 16-to-1 MUX from 4-to-1 MUXes (Cont’d.)
The first part of the file containing our 16-to-1 MUX design is straightforward. 19

20. VHDL Code for Making a 16-to-1 MUX from 4-to-1 MUXes (Cont’d.)
And here’s where we “copy and paste” five copies of mux4to1 and connect them together to make a 16-to-1 MUX.
Now note the similarity among these four statements. Can we do this more efficiently? Yes, using a GENERATE statement. 20

21. VHDL GENERATE Statement
The general form of a GENERATE statement is:
generate_label:
FOR index_variable IN range GENERATE
statement;
{statement;}
END GENERATE;
The statement(s) inside the GENERATE statement will be executed multiple times, with index_variable having a new value each time.
Most often, this statement is a component instantiation statement that “pastes” a copy of a component.
There’s another form of the GENERATE statement, different from the one shown above, but it is rarely used.

22. Using a GENERATE Statement in Our 16-to-1 MUX
In our ARCHITECTURE we can replace this: with this: 22

23. Review: Three Kinds of VHDL Assignment Statements
Here are examples of the three kinds of assignment statements we’ve studied:
Simple assignment statement y <= (NOT sel AND w0) OR (sel AND w1);
Selected assignment statement
Conditional assignment statement
As a group, these are referred to as concurrent assignment statements. 23

24. Concurrent Versus Sequential VHDL Statements
The concurrent assignment statements are adequate for the kinds of digital designs we’ve studied so far. But they’re not adequate for designs that we’ll start studying next week.
Therefore VHDL provides additional assignment statements known collectively as sequential assignment statements.
The two kinds that we’ll study are:
IF statements (similar to conditional assignment statements)
CASE statements (similar to selected assignment statements) 24

25. PROCESS Statement
IF statements and CASE statements (as well as other kinds of sequential statements) can only appear inside a PROCESS statement. General form of PROCESS statement:
PROCESS [(signal_name {, signal_name})]
{VARIABLE declaration}
BEGIN
{Simple assignment statement}
{IF statement}
{CASE statement}
{VARIABLE assignment statement}
{Other kinds of sequential statements}
END PROCESS;
Sensitivity list
The statements inside the PROCESS will execute whenever there’s a change in the value of a signal named in the sensitivity list. 25

26. IF Statement (also called an IF-THEN-ELSE Statement)
The general form of an IF statement is:
IF logic_expression THEN
statement;
{statement;}
{ELSIF logic_expression THEN
{statement;}}
[ELSE
{statement;}]
END IF;
Remember, an IF statement can only appear inside a PROCESS statement.

27. IF Statement: Example Here’s another way to implement a 2-to-1 MUX.
This sensitivity list causes the code inside this PROCESS to be executed when (and only when) there’s a change in the value of w0 or w1 or s.

28. CASE Statement The general form of a CASE statement is:
CASE expression IS
WHEN constant =>
statement;
{statement;}
{WHEN constant =>
{statement;}}
[WHEN OTHERS =>
{statement;}]
END CASE;
Remember, a CASE statement can only appear inside a PROCESS statement.

29. CASE Statement: Example
Yet another way to implement a 2-to-1 MUX!
This sensitivity list causes the code inside this PROCESS to be executed when (and only when) there’s a change in the value of w0 or w1 or s.

30. Confused Yet?
Don’t feel bad if you’re confused as to why we need all of these different kinds of statements.
For a simple 2-to-1 MUX, and for the other designs we’ve studied, the IF statement and CASE statement are overkill, more complicated than we need. You should instead use a selected assignment statement or a conditional assignment statement.
But we’ll need the added power of IF and CASE statements for future designs.

31. Which One Should I Use: CASE or IF?
As with selected signal assignments and conditional signal assignments, CASE statements and IF statements are similar to each other, and in many situations you could use either one.
But there are differences, and you’ll come to recognize cases where one type is preferable over the other.
For example, CASE statements must cover every possible case, but IF statements need not do so….

32. Which One Should I Use: CASE or IF? (Cont’d.)
Recall the general form of a CASE statement:
The cases listed here must cover every possible value of expression.
Therefore, the following statement is illegal, since it does not cover the case where s = CASE s IS
WHEN '0' => f <= w0;
END CASE;

33. Which One Should I Use: CASE or IF? (Cont’d.)
Now recall the general form of an IF statement:
The cases listed here need not cover every possible case.
So the following statement is legal, even though it doesn’t cover the case where s = IF s = '0' THEN
f <= w0;
END IF;
BUT BE CAREFUL….

34. Caution: Implied Memory
Since the IF statement on the previous slide does not cover all possible cases, a tricky point arises. Our book refers to this point as “implied memory”; other books may use other terms, such as “inferred latches.”
If you try to compile that IF statement in Quartus, you’ll succeed, but Quartus will issue this warning message: inferring latch(es) for signal or variable "f", which holds its previous value in one or more paths through the process.
What does it mean?...

35. Caution: Implied Memory (Cont’d.)
We can’t fully understand what it means until we’ve studied latches. But the point to be aware of is that Quartus assumes that in the case above, you want f to retain its previous value (whatever that is) if s is not equal to 0.
This assumption forces Quartus to insert an element called a latch into your design, which may not have been your intention when you wrote that code.
The lesson: be on your toes when using IF statements that don’t cover all possible cases.