Introduction to Programmable Logic FYSIKUM Nordic detector school FPGA introduction Introduction to VHDL Implementation design flow Digital Systemkonstruktion - 1

Digital Systemkonstruktion - 1 FPGA Structure Logic block I/O block Interconnects Digital Systemkonstruktion - 1

FPGA Logic Block (idealized) Register MUX 4-input look up table (LUT) implements combinatorial logic Register optionally stores output of LUT Digital Systemkonstruktion - 1

Field-Programmable Gate Arrays Xilinx Spartan-3 die image. Note the regularity Easily seen is the very regular structure; this is major advantage in scaling. Note also IO buffers and configuration logic on periphery. Not shown is this model is the emerging presence of significant hard IP: hard processors (PPC, ARM) multipliers block memory, so called “diffused memory” multi-gigabit transceivers highly selectable IO: LVDT, multiple voltage standards, etc. Column based datapath components becoming important as DSP application migrate to FPGAs Digital Systemkonstruktion - 1

Digital Systemkonstruktion - 1 Other FPGA features: Dedicated block memories Dual-port static RAM Digital clock management/synthesis Dedicated multipliers Important for digital signal processing "Hard" CPU cores Xilinx: PowerPC, ARM 9 Altera: Nios (Stratix II) Multi-Gbit transceivers Digital Systemkonstruktion - 1

Digital Systemkonstruktion - 1 For this course: Device: Xilinx FPGA (Spartan 3E) Design language: VHDL Simulation tool: Xilinx iSim Implementation: Xilinx ISE These are specific choices, but…. Overall contents are similar to other environments Not very difficult to transfer skills Digital Systemkonstruktion - 1

Digital Systemkonstruktion - 1 VHDL introduction VHSIC Hardware Description Language (VHSIC: Very high speed integrated circuit) Both concurrent and sequential operations International standard (1987, 1993, 2002) Pure language definition Large standard, with multiple ways to code the same behavior Digital Systemkonstruktion - 1

Design unit (library unit) Inputs/outputs (entity) In most basic form, defines Inputs/outputs (entity) Function of unit (architecture) Can be instantiated and connected together in higher level design units. Function (architecture) Digital Systemkonstruktion - 1

Digital Systemkonstruktion - 1 VHDL design unit Package Shared definitions Optional Assign specific design entities or architectures to be used in specific places Configuration Entity Inputs and outputs Architecture Description of design Process Sequential statements Digital Systemkonstruktion - 1

Multiplexer entity library ieee; use ieee.std_logic_1164.all; entity Mux is port( a: in std_logic; b: in std_logic; sel: in std_logic; y: out std_logic ); end Mux; Y SEL A B no semicolon after last port declaration! Port name Direction Type Digital Systemkonstruktion - 1

An architecture (many ways to do this) SEL A B architecture arch3 of Mux is begin y <= a when sel='0' else b; end arch3; Digital Systemkonstruktion - 1

Digital Systemkonstruktion - 1 Complete design unit: -- -- A 2 input multiplexer circuit library ieee; use ieee.std_logic_1164.all; entity Mux is port( a: in std_logic; b: in std_logic; sel: in std_logic; y: out std_logic ); end Mux; architecture arch2 of Mux is begin y <= a when sel='0' else b; end arch2; Y SEL A B Digital Systemkonstruktion - 1

Xilinx design environment (ISE) Project Navigator is now the common front end for all the ISE products, including ISE Alliance. Project Navigator is a robust and easy-to-use GUI driven design management environment that lets you see what files are involved in your design, what stages the design has already gone through, and what steps are left to completion. Project Navigator quickly and easily automates the programmable design flow. ISE 4.2i is the first programmable design software supporting Linux. Using Linux RedHat version 7.2 with the WINE applications layer, customers now have expanded operating system options. ISE 4.2i Linux is available for ISE Foundation and ISE Alliance and includes the command line implementation tools only. Future versions of ISE will include more design tools and native Linux support in 2003. So, how do you use it? Digital Systemkonstruktion - 1

Digital Systemkonstruktion - 1 Create a new project Digital Systemkonstruktion - 1

Select device, design flow Digital Systemkonstruktion - 1

Digital Systemkonstruktion - 1 Create new source Click here Or right-click here for menu Digital Systemkonstruktion - 1

Digital Systemkonstruktion - 1 New source options Digital Systemkonstruktion - 1

Digital Systemkonstruktion - 1 Initial definitions Digital Systemkonstruktion - 1

Digital Systemkonstruktion - 1 Edit sources Digital Systemkonstruktion - 1

Target to your hardware Digital Systemkonstruktion - 1

Digital Systemkonstruktion - 1 Define constraints In this case, only I/O needs to be declared. More complex designs also need info on timing constraints Digital Systemkonstruktion - 1

User Constraint File (UCF) Digital Systemkonstruktion - 1

Digital Systemkonstruktion - 1 Implement the design ISE follows the design flow up to the selected point. Digital Systemkonstruktion - 1

Digital Systemkonstruktion - 1 Configure the FPGA Digital Systemkonstruktion - 1