1. LAB #4 Xilinix ISE Foundation Tools VHDL Design Entry “A Tutorial”
ENG2410 Digital Design
LAB #4 Xilinix ISE Foundation Tools
VHDL Design Entry
“A Tutorial”

2. Lab Objectives Learn the basics of Xilinx ISE tool.
Enter your design using VHDL
Implement a 4 input function on the NEXYS 3 (Spartan 6) board.
Test/Debug your design and verify software simulation and hardware implementation.
ENG241/ Lab #4

3. VHDL Design Entry
In this Lab you will use VHDL for design entry of the following function:
Simulate your design.
Implement your Design and download it into the NEXYS 3 (Spartan 6) board.
ENG241/ Lab #4

4. Sample VHDL code library IEEE; use IEEE.STD_LOGIC_1164.ALL;
entity func1 is
port ( a,b : in std_logic;
f : out std_logic);
end func1;
architecture dataflow of func1 is
begin
f <= a or (not b);
end dataflow;
ENG241/ Lab #4

5. UCF File
It is used to define the Input/Output pin assignment for the FPGA on the NEXYS 3 board.
You will use the following assignments for the lab:
NET A LOC = T5; // left most slide switch on NEXYS 3 board
NET B LOC = V8 ; // next slide switch on NEXYS 3 board
NET C LOC = U8; // third slide switch on NEXYS 3 board
NET D LOC = N8; // fourth slide switch on NEXYS 3 board
NET E LOC = T11; // left most LED on NEXYS 3 board
ENG241/ Lab #4

6. Academic Misconduct
Reports and demos are submitted as a group, but it is a SINGLE group effort
You may talk with other groups but sharing codes or reports is NOT ALLOWED
Copying reports from previous years is also NOT ALLOWED
If we find copying we are REQUIRED to report it
ENG241/ Lab #4