Reg and Wire:

Wire: Wires are simple wires/busses of arbitrary width used in Verilog. They connect to input & output ports of a module instantiation together w/ some other element, but also within actual module declaration. Wires can’t store value, & can’t be used on the left-hand side of =/<= sign in an always@ block.(always@ blocks are used to describe events that should happen under certain conditions) Only legal type on the left-hand side of an assign statement, and wires can only be used to model combinational logic.

Wire used in Verilog: And gate. module wire_example( a, b, y); input a, b; output y; wire a, b, y; assign y = a & b; endmodule This means that if you declare a variable w/ specifying reg or wire, it will be a 1-bit wide wire.

Reg: Similar to wires, but instead store information like a container. Allowed to be connect to the input port of a module, but not the output of an instantiation. W/in a module declaration reg can be connected to the outputs, but not the inputs. Legal only on the left-hand of an always@ block =/<= sign and initial block = sign. Can’t be used on the left hand side of an assign statement, but could be used to create registers when used in conjunction w/ always@(posedge Clock) blocks. Also can be used to create both combination & sequential logic.

Reg in Verilog: Combinational Gives same output as the assign statement, but difference is the y is declared as reg. The advantages are with reg is its useful when “case” statement is required. module reg_ex ( a, b, y); input a, b; output y; reg y; wire a, b; always @ ( a or b) begin y = a & b; end endmodule Combinational