HDL simulation and Synthesis (Marks16) CH.5 HDL simulation and Synthesis (Marks16) Visit for more Learning Resources

Event Scheduling Event is a change observed in any signal and the method used for updating a new value by certain amount of delay (finite time) is termed as event scheduling. Event is nothing bue change on target signal which is updated. Example- X<= a after 05ns when select=0 else x<= b after 0.5ns. The assignment to signal ‘X’ does not happen instantly. Each of the values assigned to X contain the new value for signal x. When the event matures, signal receives a new value.

Continued…. Event occurs at different times. In VHDL, event queue is divided into five regions. Each event is added in one of the five regions but thay are removed from queue. Active event Inactive Event Non blocking assign update events Monitor Events Future Events Processing all active events is called simulation cycle.

Sensitivity List The sensitivity list is a list of the signals that will cause the process to execute. It is compact way for specifying the set of signals, events on which process resumes. every concurrent statement has a sensitivity list. Statement are executed only when there is an event or signal in sensitivity list, otherwise they are suspended . The sensitivity list is equivalent to the wait on statement, which is the last statement of the process statement section. The process statement can have explicit sensitivity list. This list defines the signals that cause the statement inside the process statement to execute whenever one or more elements of the list change value.

Continued… The sensitivity list is specified right after the key process Ex. Process(CLK,sel).

Zero Modeling The ordering of zero delays events is handled with a functionality unit called delta time. Delta delay represents the execution of a simulation cycle without advancing simulation time. The simulator models zero delay events using delta time. Events scheduled at the same time are simulated in specific order during delta time step. while describing any system for synthesis circuit delays are determined by the target technology. All digital circuit elements have a delay even if it is very short.

Continued…. The ‘0’ ns delta delay has a little impact while writing VHDL code for synthesis. But it must be included so that all circuits will be realizable. The physical circuit always have finite delays. In VHDL zero delay components which could never built. Specifying zero delay events must be orderedto produce consistence result. VHDL delays- Transport -- prescribes propagation delay only 􀂄 Inertial -- prescribes minimum input pulse width and propagation delay 􀂄 Delta -- the default, if no delay time is explicitly specified

Simulators Software used for simulation is called simulator. Classification of simulator- Logic simulator HDL based Emulator based schematic based Event Based Cycle based Gate system

The process of all active events is called simulation cycle. Delay Start Simulation Execute Process Update signals End Simulation

Continued… A VHDL simulation cycle consists of the following steps: The current time, t c is set equal to t n . Each active signal in the model is updated and events may occur as a result. For each process P, if P is currently sensitive to a signal S, and an event has occurred on signal S in this simulation cycle, then process P resumes. Each resumed process is executed until it suspends. The time of the next simulation cycle, t n , is set to the earliest of:  a. the next time at which a driver becomes active or b. the next time at which a process resumes

Continued…. If t n = t c , then the next simulation cycle is a delta cycle . Simulation is complete when we run out of time ( t n = TIME'HIGH ) and there are no active drivers or process resumptions at t n (there are some slight modifications to these rules involving postponed processes—which we rarely use in ASIC design). Time in an event-driven simulator has two dimensions. A delta cycle takes delta time , which does not result in a change in real time. Each event that occurs at the same time step executes in delta time. Only when all events have been completed and signals updated does real time advance to the next time step

Continued… Simulation cycle having three stages- 1.Analysis 2. Elaboration 3. Excution 1.Analysis In the first stage , the VHDL description of a system is checked for various kinds of errors. It is possible to analyze design units such as entity ,Architecture, body declarations separately . If analyzer finds no errors in design unit, it creates an intermediate representation of the unit and stores it in a library. The exact mechanism varies between VHDL tools .

Elaboration The second stage in simulating a model elaboration is a collection of signals and processes with each process possibly containing variables. A model must be reducible to a collection of signals and processes in order to simulate it.

Event based Simulation Event: change in logic value at a node, at a certain instant of time  (V,T) Event-driven: only considers active nodes Efficient Performs both timing and functional verification All nodes are visible Glitches are detected Most heavily used and well-suited for all types of designs

Continued… Event: change in logic value, at a certain instant of time  (V,T)

Continued…

Comparison Of Software and Hardware Language For more detail contact us