1. Timing & Concurrency II
How do you achieve deterministic concurrent simulation. More examples and delta delay.
1/8/ L15 Timing & Concurrency II
Copyright Joanne DeGroat, ECE, OSU

2. Overview – Timing & Concurrency
Delta delay
More examples to include processes
Simulation Techniques
The VHDL Simulation Cycle
1/8/ L15 Timing & Concurrency II
Copyright Joanne DeGroat, ECE, OSU

3. Copyright 2006 - Joanne DeGroat, ECE, OSU
Delta Delay
Delta Delay – when transactions occur in “0” time, the pseudo-concurrent environment schedules then in Delta time. (d)
ENTITY dt_example IS
PORT( a,b,c : IN BIT; z : OUT BIT);
END dt_example;
ARCHITECTURE from_book OF dt_example IS
SIGNAL w, x, y : BIT := ‘0’;
BEGIN
y <= c AND w;
w <= NOT a;
x <= a AND b;
z <= x OR y AFTER 36 ns;
END from_book;
This example will be use to examine delta delay
1/8/ L15 Timing & Concurrency II
Copyright Joanne DeGroat, ECE, OSU

4. Transactions generated at t=0
a, b, and c come in through the port and have an initial value of ‘1’
Externally there is a signal assignment statement a <= ‘0’; which gets executed at t=0 and generates the transaction a(‘0’,0, d, d)
Concurrent signal assignment statements in architecture are evaluated at t=0. Not that a,b,c all have current value ‘1’
1/8/ L15 Timing & Concurrency II
Copyright Joanne DeGroat, ECE, OSU

5. Transaction from the architecture
Signals of architecture are initial value of ‘0’
TIME 0 transcations
y(‘0’,0,+1d, +1d)
w(‘0’,0, +1d, +1d)
x(‘1’,0, +1d, +1d)
z(‘0’,0, 36, 36)
AND FROM EXTERNALLY generated transaction
a(‘0’,0,+1d, +1d)
Now will advance time till the next time at which something occurs which is 1d
1/8/ L15 Timing & Concurrency II
Copyright Joanne DeGroat, ECE, OSU

6. Copyright 2006 - Joanne DeGroat, ECE, OSU
t=0 waveform
waveform
1/8/ L15 Timing & Concurrency II
Copyright Joanne DeGroat, ECE, OSU

7. Copyright 2006 - Joanne DeGroat, ECE, OSU
First action is at +1d
Action at 0+1d
Post values for w,x,y,a
Posting of a and x results in an event on both
Processes (concurrent signal assignment stmt) sensitive to a and x are then re-evaluated
1/8/ L15 Timing & Concurrency II
Copyright Joanne DeGroat, ECE, OSU

8. Re-eval of sensitive to a
Concurrent statements sensitive to a and x are signal assignment statement for w, x and z.
Evaluation causes generation of new transaction for w, x, and z
Current value at t=+1d are a=0 b=1 x=1 y=0
Generate transactions
w(‘1’, +1d, +1d, +2d)
x(‘0’, +1d, +1d, +2d)
z(‘1’, +1d,36,36)
1/8/ L15 Timing & Concurrency II
Copyright Joanne DeGroat, ECE, OSU

9. Copyright 2006 - Joanne DeGroat, ECE, OSU
Transaction for z
Event Queue for Z before posting
z(‘0’,0, 36, 36)
Transaction to be posted
z(‘1’,+1d,36,36)
“Transaction for a driver on the projected output waveform queue that occur at or after the transaction to be posted are deleted”
Event Queue for z after posting as existing 36ns transaction is deleted
1/8/ L15 Timing & Concurrency II
Copyright Joanne DeGroat, ECE, OSU

10. Progressing forward to +2d
Transaction list
z(‘1’, +1d, 36, 36)
w(‘1’, +1d, +1d, +2d)
x(‘0’, +1d, +1d, +2d)
x and w have events
Re-eval y and z which generate
y(‘1’, +2d, +1d, +3d)
z(‘0’, +2d, 36, 36)
1/8/ L15 Timing & Concurrency II
Copyright Joanne DeGroat, ECE, OSU

11. Progressing forward at +3d
Transaction list
y(‘1’, +2d, +1d, +3d)
z(‘0’, +2d, 36, 36)
event on y
Re-eval z which generates
z(‘1’, +3d, 36, 36)
1/8/ L15 Timing & Concurrency II
Copyright Joanne DeGroat, ECE, OSU

12. Copyright 2006 - Joanne DeGroat, ECE, OSU
And the final result
Post the final transaction for z
z(‘1’, +3d, 36, 36)
Does not result in an event
Simulation goes quiescent if testbench does
1/8/ L15 Timing & Concurrency II
Copyright Joanne DeGroat, ECE, OSU

13. Delta delays and process waits
Lets now examine another example that highlights processes and sequential signal assignment statements.
1/8/ L15 Timing & Concurrency II
Copyright Joanne DeGroat, ECE, OSU

14. Delta delay with processes
ENTITY timing IS END timing;
ARCHITECTURE concurrent2 OF timing IS
SIGNAL a,b,c : BIT := ‘0’;
BEGIN
A: PROCESS
a <= b;
WAIT FOR 10 ns;
END PROCESS A;
B: PROCESS
VARIABLE d : BIT :=‘0’;
BEGIN
b <= d AFTER 1 ns;
d := c;
WAIT FOR 5 ns;
c <= ‘1’;
END PROCESS B;
END concurrent2;
1/8/ L15 Timing & Concurrency II
Copyright Joanne DeGroat, ECE, OSU

15. Copyright 2006 - Joanne DeGroat, ECE, OSU
Initial values
Initail value of all signals is ‘0’
Evaluate all processes until they suspend A:
a(‘0’,0,+1d,+1d)
A suspends until 10 ns; B:
b(‘0’,0,1,1)
var d set to ‘0’
B suspends until 5 ns;
1/8/ L15 Timing & Concurrency II
Copyright Joanne DeGroat, ECE, OSU

16. Copyright 2006 - Joanne DeGroat, ECE, OSU
Advance time to 1d
Transaction to post
a(‘0’,0,+1d,+1d)
Causes no other action
Have processes suspended
A till 10 ns
B till 5 ns
1/8/ L15 Timing & Concurrency II
Copyright Joanne DeGroat, ECE, OSU

17. Copyright 2006 - Joanne DeGroat, ECE, OSU
Advance time to 1 ns
Post last transaction on queue
b(‘0’,0,1,1)
Causes no other action
Have processes suspended
A till 10 ns
B till 5 ns
1/8/ L15 Timing & Concurrency II
Copyright Joanne DeGroat, ECE, OSU

18. Copyright 2006 - Joanne DeGroat, ECE, OSU
Advance to 5 ns
Resume PROCESS B from where it suspended
Generates transaction
c (‘1’,5ns,+1d,5+1d)
Variable d is reassigned to ‘0’
B suspends until 10 ns
1/8/ L15 Timing & Concurrency II
Copyright Joanne DeGroat, ECE, OSU

19. Copyright 2006 - Joanne DeGroat, ECE, OSU
Advance to 5+1d ns
Post transaction
c (‘1’,5ns,5+1d,5+1d)
causes an event
PROCESSES Suspended
A till 10 ns
B till 10 ns
1/8/ L15 Timing & Concurrency II
Copyright Joanne DeGroat, ECE, OSU

20. Copyright 2006 - Joanne DeGroat, ECE, OSU
Advance to t = 10 ns
Process A and B resume A:
a(‘0’,10, +1d,10+1d)
A suspends till 20 ns; B:
b(‘0’,10,1,11)
d set to ‘1’
B suspends till 15 ns;
1/8/ L15 Timing & Concurrency II
Copyright Joanne DeGroat, ECE, OSU

21. Copyright 2006 - Joanne DeGroat, ECE, OSU
Advance to t = 10+1d
Post transaction
a(‘0’,10, +1d,10+1d)
No other action
1/8/ L15 Timing & Concurrency II
Copyright Joanne DeGroat, ECE, OSU

22. Copyright 2006 - Joanne DeGroat, ECE, OSU
Advance to 11 ns
Post transaction
b(‘0’,10,1,11)
No other action
1/8/ L15 Timing & Concurrency II
Copyright Joanne DeGroat, ECE, OSU

23. Copyright 2006 - Joanne DeGroat, ECE, OSU
Advance to t = 15 ns
B resumes
c (‘1’,15, +1d,15+1d)
d set to c or ‘1’
B suspends till 20 ns;
1/8/ L15 Timing & Concurrency II
Copyright Joanne DeGroat, ECE, OSU

24. Copyright 2006 - Joanne DeGroat, ECE, OSU
Action at t =15+1d
Post transaction
c (‘1’,15, +1d,15+1d)
1/8/ L15 Timing & Concurrency II
Copyright Joanne DeGroat, ECE, OSU

25. Copyright 2006 - Joanne DeGroat, ECE, OSU
Advance to t = 20 ns
A resumes
a(‘0’,20, +1d,20+1d)
A suspends till 30 ns
B resumes at top
b(‘1’,20,1,21)
d set to ‘1’
B suspends until 25
1/8/ L15 Timing & Concurrency II
Copyright Joanne DeGroat, ECE, OSU

26. Copyright 2006 - Joanne DeGroat, ECE, OSU
Action at t= 20 and 21
Post transactions
a(‘0’,20, +1d,20+1d)
b(‘1’,20,1,21)
This is not the end of the action of the simulation
Simulation never goes quiescent as there are always processes suspended
1/8/ L15 Timing & Concurrency II
Copyright Joanne DeGroat, ECE, OSU