1. 2-Jun-16EE5141 Chapter 3 ä The concept of the signal ä Process concurrency ä Delta time ä Concurrent and sequential statements ä Process activation by a signal event ä Signal-valued & signal-related attributes ä Exercises

2. 2-Jun-16EE5142 The concept of the signal Signal functions as connection line which transfers information between circuit parts  Signal properties present and future values timing delay event and transaction signal driver and signal resolution  Multiple drivers

3. 2-Jun-16EE5143 Process concurrency ä NANXOR code entity NANDXOR is port ( port ( A, B : in bit; A, B : in bit; C : in bit; C : in bit; D : out bit); D : out bit); end NANDXOR; architecture RTL of NANDXOR is signal T : bit; signal T : bit;begin p0 : T <= A nand B after 2 ns; p0 : T <= A nand B after 2 ns; p1 : process (T, C) p1 : process (T, C) begin begin D <= T xor C after 3 ns; D <= T xor C after 3 ns; end process p1; end process p1; end RTL;

4. 2-Jun-16EE5144 Process concurrency Signal T:bit; Defines T as the connection signal between NAND and OR gates. Initialization: signals set to their default (left most for their type) values Each process is evaluated and then suspended ActiveSuspended Running Select a process by a scheduler Signal event Update signal value Execution complete

5. 2-Jun-16EE5145 Process concurrency architecture RTL of NANDXOR is signal T : bit; begin p0 : T <= A nand B after 2 ns; p1 : process (T, C) begin D <= T xor C after 3 ns; end process p1; end RTL;

6. 2-Jun-16EE5146 Delta time architecture DELTA of NANDXOR is signal T : bit; begin p0 : T <= A nand B; p1 : process (T, C) begin D <= T xor C; end process p1; end DELTA;

7. 2-Jun-16EE5147 Delta time ä Compare Figures 3.5 & 3.6

8. 2-Jun-16EE5148 Delta time ä Waveforms at time 30

9. 2-Jun-16EE5149 Delta time Processes p0, p1 have no time delay, but if the simulator continues to increase the delta delay, the delta goes up infinitely and the simulator may go into an infinite loop. Processes p0, p1 have no time delay, but if the simulator continues to increase the delta delay, the delta goes up infinitely and the simulator may go into an infinite loop.

10. 2-Jun-16EE51410 Concurrent & sequential statements ä Concurrent statements ä Sequential statements if statement case and loop statements procedure call statement assert statement signal assignment statement variable assignment statement null, exit, and wait statements return and next statements block statement process statement generate statement procedure call statement assert statement signal assignment component instantiation

11. 2-Jun-16EE51411 Concurrent & sequential statements VHDL coding rules ä Only concurrent statements can be inside the architecture statement part. ä Sequential statements can only appear inside the procedure and function body and inside the process statement. ä Signals are used to communicate among concurrent processes. ä Local variables can only be declared inside the procedure and function body and the process statement. They are not visible outside of the procedure, function, and process statement.

12. 2-Jun-16EE51412 Concurrent & sequential statements ä Architecture VHDL code entity OVERALL is end OVERALL architecture RTL of OVERALL is --architecture declarative part begin --architecture statement part end RTL;

13. 2-Jun-16EE51413 Concurrent & sequential statements

14. 2-Jun-16EE51414 Process activation by a signal event architecture SLIST of NANDXOR is signal T : bit; signal T : bit;begin p0 : T <= A nand B; p0 : T <= A nand B; p1 : process (T) p1 : process (T) begin begin D <= T xor C; D <= T xor C; end process p1; end process p1; end SLIST;

15. 2-Jun-16EE51415 Process activation by a signal event T is the sensitivity list of the p1 process (line 5 of SLIST architecture). Process is activated by a signal T event. A process statement requires an explicit wait statement or a process sensitivity list but not both. A process statement requires an explicit wait statement or a process sensitivity list but not both.

16. 2-Jun-16EE51416 Process activation by a signal event Wrong simulation waveforms of the SLIST

17. 2-Jun-16EE51417 Signal-valued & signal-related attributes ä SIG’delayed(T) defines a signal which is the signal SIG delayed by time T. T=0 ns is the default if parameter T is not specified. ä SIG’stable(T) defines a BOOLEAN signal whose value is TRUE if signal SIG has not had an event for the length of time T. T=0 ns is the default if parameter T is not specified. SIG’stable would be FALSE during the simulation cycle when SIG is changed and then returns to TRUE.

18. 2-Jun-16EE51418 Signal-valued & signal-related attributes ä SIG’quiet(T) defines a BOOLEAN signal whose value is TRUE if signal SIG has not had an transaction (not active) for the length of time T. T=0 ns is the default. SIG’quiet would be FALSE during the simulation cycle when SIG is assigned to and then returns to TRUE. ä SIG’transaction defines a BIT signal whose value toggles each time a transaction occurs on signal SIG.

19. 2-Jun-16EE51419 Signal-valued & signal-related attributes ä SIG’event is a BOOLEAN typed attribute. It is true if an event occurs on signal SIG during the current simulation cycle. ä SIG’active is a BOOLEAN typed attribute. It is true if a tranction occurs on signal SIG during the current simulation cycle. ä SIG’last_event is a TIME typed attribute. It returns the amount of time elapsed since the last event on signal SIG.

20. 2-Jun-16EE51420 Signal-valued & signal-related attributes ä SIG’last_active is a TIME typed attribute.It returns the amount of time elapsed since the last transaction on signal SIG. ä SIG’last_value returns the value of signal SIG before the last event on signal SIG.

21. 2-Jun-16EE51421 Exercises entity RUNAWAY is port ( port ( X : in bit; X : in bit; Z : out bit); Z : out bit); end RUNAWAY; Is it possible for a VHDL simulator to run forever without advancing simulation time? For example, Figure 3.13 shows a NAND gate with its output connecting to one of its inputs architecture RTL of RUNAWAY is signal T : bit; signal T : bit;begin T <= X nand T; T <= X nand T; Z <= T; Z <= T; end RTL;