Solar Probe Plus – FIELDS Main Electronics Package Instrument Pre-Ship Review Digital Fields Board (DFB) David Malaspina LASP, University of Colorado David.malaspina@lasp.colorado.edu 10 April 2017

DFB FM2 Hardware Photos Top Bottom

DFB Performance – Gain / Phase Gain / Phase Performance Meets Requirements on all 26 channels (gain < +/- 0.1 dB from design, -3 dB @ 80% Nyquist, minimal phase distortion in-band, steady response over temperature, minimal variation between like channels) SCM Example: SCM z Low Frequency, High Gain

DFB Performance – Noise Noise Performance Meets Requirements (minimal variation over temperature, similar on like channels, dominated by SIDECAR ASIC) [Caveat: SCM end-to-end noise level to be verified at S/C assembly level]

DFB Performance – Offset Offset Performance Meets Requirements (minimal variation over temperature, simply calibrated out on flight)

DFB Performance – Crosstalk Crosstalk Performance Meets Requirements (characterized over temperature, worst case is 54.38 dB V5 DC to E34 DC HG)

DFB Performance – Total Harmonic Distortion Harmonic Distortion Performance Meets Requirements (characterized over temperature, most better than -70 dB, worst case is -61.3 dB)   Total Harmonic Distortion (dBc) Gain State -25°C Room Temp 55°C 70°C BX_MF_HG -73.821007 -77.159659 -68.773826 -61.315422 BY_LF_HG -79.831712 -84.073972 -71.016277 -62.234124 BY_LF_LG -70.636992 -74.117294 -74.007189 -71.161934 BZ_LF_LG -73.988616 -78.404136 -78.202683 -74.648779 BZ_LF_HG -76.463665 -79.863677 -69.539469 -61.568144 BX_LF_LG -79.999873 -86.000058 -83.451167 -77.533977 BX_LF_HG -75.947437 -78.983111 -69.972038 -62.167183 V1_AC -76.4204 -77.328829 -76.847457 -75.60987 E12_AC -73.358041 -76.713549 -77.978197 -77.910809 V2_AC -73.398466 -75.551832 -75.710232 -74.810496 V1_DC -78.54245 -83.621698 -81.685076 -76.292903 E12_DC_HG -88.995651 -87.001805 -77.398549 -66.922733 E12_DC_LG -72.928249 -70.852162 -69.643699 -69.009924 V2_DC -68.656252 -72.662291 -73.507997 -71.88438 V3_AC -72.870713 -75.400036 -75.546948 -74.377786 E34_AC -72.534099 -76.551188 -77.26587 -76.026058 V4_AC -74.538404 -76.136059 -76.094035 -75.054617 V3_DC -76.05761 -79.273392 -77.942444 -74.381945 E34_DC_HG -78.319953 -80.633204 -78.890798 -66.83056 E34_DC_LG -69.508021 -69.978995 -68.870558 -67.835102 V4_DC -77.156873 -80.444087 -79.954342 -76.912439 V5_AC -73.731375 -75.703035 -75.387551 -74.564933 EZ_AC -77.390528 -78.495053 -78.721822 -78.187984 V5_DC -76.105184 -79.785031 -79.238673 -75.761356 EZ_DC_HG -71.817568 -75.867694 -70.156379 -63.977987 EZ_DC_LG -72.750517 -70.71996 -69.4566 -68.766653

DFB Performance – FPGA All FPGA algorithms verified FPGA functions Signal Averaging Timing Synchronization Data Compression Digital Housekeeping CCSDS Data Packetization FPGA DSP Functions/Data Products FFT Spectral and Cross-Spectral Processing Digital Filters Digital Burst Memory Band-Pass Filter Banks Waveforms Spacecraft Potential Fields Probe/Processing Control 16 Programmable modes Modes are loaded from the DCB at power on All FPGA algorithms verified through board-level testing (compared end-to-end results with independently calculated results from IDL models) Production and distribution of DFB data products in flight configurations verified during MEP-level testing Flight-configuration DFB modes + register tables verified during MEP-level testing

DFB Readiness DFB is complete, integrated and tested in the MEP, and ready to ship DFB FM02 integrated in MEP and performing as specified DFB team supported MEP environmental testing FM2 EIDP complete and delivered to FIELDS SMA No outstanding RFAs/risks/actions, NCRs/waivers closed, drawings released DFB FM01 (flight spare) calibration testing complete and performing as specified Completed DFB L4 verification requirements reports

DFB PSR DFB Backup Slides

DFB Block Diagram

DFB FPGA DIAGRAM

DFB Performance – Frequency Response Gain / Phase response E AC Example: E34 AC

DFB Performance – Frequency Response Gain / Phase response E DC Example: E12 DC

DFB Performance – Frequency Response Gain / Phase response V AC Example V1 AC

DFB Performance – Frequency Response Gain / Phase response V DC Example V5 DC

DFB Performance – Frequency Response EDCLG Sample Plots EZDCLG

DFB Performance – Frequency Response BLG Sample Plots BxLFLG

DFB Performance – Noise Noise Performance Meets Requirements (minimal variation over temperature, similar on like channels, dominated by SIDECAR ASIC) [Caveat: SCM end-to-end noise level to be verified at S/C assembly level]

DFB Performance – Noise Noise Performance Meets Requirements (minimal variation over temperature, similar on like channels, dominated by SIDECAR ASIC) [Caveat: SCM end-to-end noise level to be verified at S/C assembly level] Non-flight SCM just misses Requirement Need flight SCM test

DFB Performance – Noise Noise Performance Meets Requirements (minimal variation over temperature, similar on like channels, dominated by SIDECAR ASIC) [Caveat: SCM end-to-end noise level to be verified at S/C assembly level]

DFB Performance - End to End CMRR Common Mode Rejection Ratio (CMRR) Performance Meets Requirements (characterized over frequency and temperature, similar on like channels) Worst case in-band CMRR Temperature (°C) E AC 12 E AC 34 E AC z E DC 12 HG E DC 34 HG E DC z HG E DC 12 LG E DC 34 LG E DC z LG +20 62.56 59.74 40.05 75.65 52.84 49.25 78.75 52.93 49.20 +55 68.36 62.87 40.33 72.52 52.54 49.49 73.40 52.65 49.37 +70 77.62 60.66 40.10 74.98 51.46 49.27 71.96 52.51

DFB Performance – Nominal Linearity -60 dBFS 66 DN -70 dBFS 21 DN -80 dBFS 6.6 DN

DFB Performance – ASIC (ADCs) ASIC verification SIDECAR ASIC ADCs can sample up to 32 channels @ 150,000 S/s DFB uses 26 of these ASIC performance characterized, flight channels selected ASIC performance verified during DFB board-level verification (300+ FM test-hours and 600+EM test-hours) and MEP-level verification testing.

FPGA – Design Drivers Calculate FFTs on four 18.75kss channels with 100% coverage Calculate FFTs on four 150kss channels with at least 12.5% coverage Drives SRAM size and bandwidth Provide digital filtering for 16 channels of 150kS/s data and 16 channels of 18.75kS/s data Package science data into CCSDS packets Perform compression on time series waveform and DBM data Perform pseudo-log compression on Spectra, X-Spectra, and Band-Pass Filter Banks results Generate sine wave data for SCM calibration signal

FPGA Functions Fields Probe/Processing Control 16 Programmable modes Modes are loaded from the DCB at power on Signal Acquisition & Digital Filtering 26 channels sampled simultaneously at 150K samples/second AC signals: digitally filtered and decimated to produce samples from 150KS/s down to 2.3KS/s DC signals: digitally filtered and decimated to produce samples from 18.75KS/s down to 1.1S/s. DCB Interface Serial Command Interface Serial Telemetry Interface 19.2Mhz system clock 4.8Mhz telemetry clock SCM Calibration Digitally Synthesized sine wave Sine values generated via the CORDIC algorithm Sent to 16bit DAC for analog conversion

DFB Readiness DFB is complete, integrated and tested in the MEP, and ready to ship DFB FM02 integrated in MEP and performing as specified DFB meets requirements and is ready for shipment DFB team supported MEP environmental testing No outstanding RFAs/risks/actions, NCRs/waivers closed, drawings released FM2 EIDP complete and delivered to FIELDS SMA DFB FM01 (flight spare) calibration testing complete and performing as specified Completed DFB L4 verification requirements reports 6 remaining L4s to be completed at MEP level, DFB team to review results/provide concurrence L4s Total To Be Complete In Process In Review Complete DFB Specific 9 MEP-level Interfaces 15 MEP-level Environmental Test 6 L4s to complete at MEP level I&T Environmental Review Complete Function throughout perihelion x Function throughout Solar Storms Accept Loss of Power Accept Momentum Dumps Environment: survival thermal & ops limits, launch loads, random vibe, radiation environment Spacecraft EMC compliance per the EMECP

MEP-Level DFB L5s L5 Specifications 1 DFB corner frequencies for AC should be 60Khz 10 DFB sensitivity levels for all channels should be recorded 2 DFB corner frequencies for DC should be 7.5Khz 11 DFB Total Harmonic Distortion (THD), including subharmonics from sampling, with the SIDECAR ASIC should not exceed 60dB for full-scale input at DC 937hz and AC 9.37Khz 3 DFB channel to channel for AC Low Pass should be within +/- 2Khz 12 DFB THD for analog section, without SIDECAR ASIC, should be approximately 80dB for full-scale input at DC 937hz and AC 9.37Khz 4 DFB channel to channel for AC High Pass should be within +/- 10hz 13 DFB cross talk at board level should be approximately 60dB or better among E-field channel. Evaluation frequencies should be 937Hz (DC), 9.37K (AC). 5 DFB channel to channel for DC should be at same frequency at approximately +/- 500hz. Record response 14 DFB cross talk at board level should be approximately 60dB or better among B-field channels. Evaluation frequencies should be 937Hz (DC), 9.37K (AC). 6 DFB roll off should be 120dB/decade, and 36dB/octave for B-Field, and 80dB/decade for E-Field 15 DFB cross talk between any E-field and any B-field channel should be approximately 80dB or better. Evaluation frequencies should be 937Hz (DC), 9.37K (AC). 7 DFB tolerance on each pass-band gain for single-ended E-field channel should be approximately 0.5dB. Need to verify full scale input to output wrt tolerance 16 DFB CMRR should be approximately 50dBc at the input to the SIDECAR ASIC in the passband of E12 and E34 channels 8 DFB tolerance on each pass-band gain for high and low gain differential E-field and B-field channel should be approximately 0.5dB. Need to verify full scale input to output wrt tolerance 17 DFB CMRR should be approximately 50dBc end-to-end in the passband of E12 and E34 channels 9 DFB offset on each analog channel output should be 1.65V +/- 50mV at operating temp, fluctuation at temperature needs to be considered and included in expected output.