1. 1 IF Receiver for Wideband Digitally Modulated Signals Direct Instructor: Doctor Ronen Holtzman, Microwave Division, Elisra Electronic Systems Ltd. Supervising Instructor: Professor Raphael Kastner, Department of Physical Electronics, School of Electrical Engineering, Tel Aviv University Oren Avraham

2. 2 Presentation Outline Objectives Requirements Block Diagrams Processing Features Research and Reading Subjects Results and Conclusions

3. 3 Primary Objectives I. Design a receiver for wideband digitally modulated signals: Analog processing: full circuit design Digital processing: algorithm principles Software definition (including Gain and NF evaluation for BIT) II. Perform the required research and literary reading on various aspects of the analog and digital processing to assure minimal degradation in signal quality, among which are the following: Analog to Digital Converters and their proper use in the integrated system. Calculation of Sampling Clock Aperture Jitter and its effect on ADC SNR. III. Realize and test a working PCB using SMT components, which performs the analog processing section.

4. 4 System Block Diagram

5. 5 Main Requirements Input / Output Frequencies:  70 MHz  140 MHz 4 Selectable Bandwidths per Center Frequency SNR degradation (IF Cascade & ADC): 0.1 dB, maximum Maximal Dynamic Range @ 100 KHz Resolution : 2 nd Order: 70 dB, minimum 3 rd Order: 70 dB, minimum Gain Control Dynamic Range:  AGC: 30 dB  MGC: 30 dB Output Power Level: Should be chosen to best utilize the ADC’s Dynamic Range.

6. 6 Analog Processing: Block Diagram

7. 7 Automatic Gain Control Manual Gain Control Sub-Octave Filtration Anti-Aliasing Filtration Noise Injection for BIT Purposes Analog Processing: Main Features

8. 8 AGC/MGC (1): Circuit

9. 9 AGC/MGC (2): IF Detector

10. 10 AGC/MGC (3): VVA

11. 11 Performed by the Pre-Selector Filter Bank Improves the effective IP 2 by at least 20 dB Composed of Eight Band Pass Filters: 1. 70/5 MHz 2. 70/10 MHz 3. 70/28 MHz 4. 70/40 MHz 5. 140/10 MHz 6. 140/20 MHz 7. 140/40 MHz 8. 140/56 MHz A Bypass channel is included for scenarios in which an extremely low Group Delay Variation is required. Sub-Octave Filtration

12. 12 Performed by two filters: 1. LPF 90 MHz 2. BPF 140/56 MHz Designed for a Sampling Frequency of 196.608 MHz (48 th multiple of an E1 rate). Replica Rejection for worst case scenario: 1. LPF 90 MHz: 70 dBc 2. BPF 140/56 MHz: 55 dBc Anti-Aliasing Filtration

13. 13 A Noise Generator (ENR=30 dB) is used for Noise Injection ADC Samples are used as observations and two noise power levels are computed: 1. N 1 – Natural Thermal Noise at Cascade Input (-174 dBm/Hz) 2. N 2 – Generator Noise at Cascade Input (-144 dBm/Hz) Using the following equations the IF cascade’s Gain and Noise Figure are evaluated: The test scans all signal channels and produces a Pass/Fail report. Built In Test

14. 14 Digital Processing: Block Diagram

15. 15 Simplified View of Sampled Spectrum

16. 16 Research and Literary Reading Subjects: ADC-Related System Design Considerations The complete Receiver functions as an Integrated Analog- Digital System. A thorough understanding of the ADC’s effects on the integrated system’s performance is required.  This is performed by characterizing the ADC in “RF/IF terms” and designing the IF cascade accordingly. One of the main questions which arise is the following: What is the optimal power of the analog signal at the ADC ’ s input?

17. 17 It is a wide spread notion that in order to best utilize the ADC ’ s Dynamic Range (bits), the analog signal ’ s power at the ADC ’ s input should be as high as possible, putting it very close to Full Scale Power (FSP). This yields very demanding Gain and Linearity requirements of the RF cascade preceding the ADC, and causes an inevitable degradation of signal integrity (higher gain means higher intermodulation products, harmonics, likelihood of compression and so forth). Furthermore, the risk of ADC clipping (when the analog signal power exceeds its FSP) runs very high. Input Power to ADC – Introduction (1)

18. 18 Our hypothesis is that it is not the analog signal ’ s power but rather the amplified Thermal Noise of the RF/IF cascade at the ADC ’ s input which determines the degradation in system noise performance caused by the ADC. This is based on the fact that ADC noise (Thermal, Quantization and Jitter Induced) can be referred to as white noise. This white noise is added to the amplified thermal noise (which is white is as well) at the ADC ’ s input. Since both noises are white and statistically independent, the result is their power summation. Therefore, we can calculate the ADC ’ s Effective Noise Figure. Input Power to ADC – Introduction (2)

19. 19 Input Power to ADC: ADC Effective NF ADC FSP [dBm] Typically 1 dB below FSP [-1 dBFS] SNR (Integrated Over Entire Nyquist Bandwidth) [dB] Thermal Noise Density (kTB=-174 dBm/Hz ) ADC Effective NF [dB] ADC Noise Density [dBm/Hz]

20. 20 In order to perform the power summation of Thermal Noise and ADC Noise in a more intuitive manner, we use the Over Gain approximation: Input Power to ADC – OG (1) Natural Thermal Noise: -174 dBm/Hz Amplified Thermal Noise: N RF/IF ADC Noise: N ADC Combined Noise

21. 21 The different Noise Power Levels are: OG Summation Amplified Thermal Noise: N RF/IF [dBm] ADC Noise: N ADC [dBm] Combined Noise [dBm] Over Gain (OG) [dB] Δ(OG) [dB] Δ(OG) [dB] ≈ |OG| 20.04 15.1 10.4 7 3 1 0.4 0.1 0.04 ≈ 0 OG [dB] <-20 -20 -15 -10 -6 0 6 10 15 20 >20 Input Power to ADC – OG (2)

22. 22 Therefore, we can predict the ADC- Induced SNR Degradation based on the OG table. We note that for an OG of more than 15 dB, this degradation is negligible. From this, we would derive the Gain Requirement of the RF/IF Cascade (for a given NF): We verified our hypothesis by simulation, as presented in the following slides. Input Power to ADC – OG (3) OG [dB] SNR Degradation [dB] <-20≈ |OG| -2020.04 -1515.1 -1010.4 -67 03 61 100.4 150.1 200.04 >20≈ 0

23. 23 High OG (20 dB), -50 dBFS Input Sine Wave: Input Power to ADC – Simulation (1)

24. 24 Low OG (-10 dB), -1 dBFS Input Sine Wave: Input Power to ADC – Simulation (2)

25. 25 High OG (15 dB), -90 dBFS Input Sine Wave: Input Power to ADC – Simulation (3)

26. 26 OG Sweep (-30 dB to +30 dB), showing that our hypothesis coincides with the simulation results: Input Power to ADC – Simulation (4)

27. 27 IP 3 is the 3 rd order Intercept Point, which corresponds to the 3 rd order Intermodulation Products of a non-linear analog (RF) component. One of the ADC’s non-linearity parameters is the “Two-Tone Intermodulation Distortion Rejection” (IMDR). We “translate” the ADC’s IMDR to RF/IF terms (IP 3 ) using the following relation: ADC: Effective IP 3

28. 28 Effect of Sampling Clock Aperture Jitter on ADC SNR The Effective SNR of an ADC is comprised of several noise sources: Analog Signal Frequency RMS Aperture Jitter of Sampling Clock ADC Resolution (Number of bits) ADC DNL (Differential Non Linearity) Thermal Noise in LSBs

29. 29 The common approach to calculate the RMS Aperture Jitter of a frequency source (such as a sampling clock) is to integrate its Phase Noise as is, and simply translate the result (received in radians) to temporal terms (seconds): Calculation of Sampling Clock RMS Aperture Jitter (1)

30. 30 Oscillator (Center) Frequency Frequency Offset From Center Frequency Oscillator Phase Noise (After BPF) We apply a more modern approach which incorporates a sine function factor, as follows: Calculation of Sampling Clock RMS Aperture Jitter (2)

31. 31 The sine factor attenuates the Phase Noise close to the oscillator center frequency, as depicted in the following figure: Calculation of Sampling Clock RMS Aperture Jitter (3)

32. 32 Center Frequency (f s =98.304 MHz) 2f s At frequencies that are far from the center, the Phase Noise is attenuated by the Clock’s BPF: Calculation of Sampling Clock RMS Aperture Jitter (4)

33. 33 Calculation of Sampling Clock RMS Aperture Jitter (5)

34. 34 Results (1): At 70 MHz ParameterRequirement Measurement 2 nd Amp Enabled 2 nd Amp Disabled Noise Figure, maximum [dB] 9.55.28.5 Expected SNR Degradation, maximum [dB] 0.1<10 -3 0.085 DR 2 @ 100 KHz BW, minimum [dB] 7076.985.25 DR 3 @ 100 KHz BW, minimum [dB] 7072.284

35. 35 Results (2): At 140 MHz ParameterRequirement Measurement 2 nd Amp Enabled 2 nd Amp Disabled Noise Figure, maximum [dB] 9.55.59 Expected SNR Degradation, maximum [dB] 0.1<10 -3 0.095 DR 2 @ 100 KHz BW, minimum [dB] 707785.25 DR 3 @ 100 KHz BW, minimum [dB] 707283.65

36. 36 Conclusions I. The Subject of ADC Integration with RF/IF Cascades was explored, reaching the following conclusions: The ADC-Induced SNR Degradation is determined by the level of thermal noise at the ADC’s input. Even sub-LSB signals can be detected by the ADC. The Over Gain approximation proved to be a good method to determine the required Gain of the RF/IF cascade and predict the SNR Degradation. II. The Analog (IF) section of the receiver was designed, built and measured showing electrical performance surpassing the requirements.