FSSR2 verilog simulations Massimo Manghisoni XI Workshop INFN Frascati - 2 December 2009

FSSR2 block diagram The FSSR2 chip architecture is virtually identical to that of FPIX2. Each strip is treated as one pixel cell (Pseudo-Pixel architecture)[*] It can be described as including four sections FSSR2 Core 128 analog channels 16 sets of logic, each handling 8 channels (EOS Logic) Core logic with BCO counter (time stamp) Programming Interface (slow control) Programmable registers Data Output Interface 128 channels of analog circuits End-Of-Set Logic 16 Sets of logic each handling 8 analog channels CORE Core Logic Clock Control Logic PROGRAMMABLE REGISTERS Next Block Word DACs DATA OUTPUT INTERFACE PROGRAMMING INTERFACE Word Serializer Steering Logic FSSR clk I/O MCA/MCB High Speed out [*] PreFPIX2: core architecture and results Hoff, J.R.; Mekkaoui, A.; Christian, D.C.; Zimmerman, S.; Cancelo, G.; Kasper, P.; Yarema, R.; Nuclear Science, IEEE Transactions on, Volume 48,  Issue 3,  Part 1,  June 2001 Page(s):485 - 492

FSSR Clk, Master Clocks, Serial In, Out and Ctrl The FSSR2 Verilog Model 128 “Strips” Ordered by BCO 128 “Strips” With timing info 1,2,4, or 6 serial lines + Output Clk Silicon Strip Det. Model Data Outputs Monte Carlo Data FSSR Model Strip Inputs DAQ Model Report Control Inputs Silhits_2int.dat daq.v FSSR2.v stripBlocks.v stripCell.v stripEOC.v stripCore.v stripDataInt.v stripProgInt.v stripConstants.v daq.v fStripDat.out FSSR Clk, Master Clocks, Serial In, Out and Ctrl List Of Originals Recorded Events, Misses, Matches fStripOut.out fStripMatch.out fStripMis.out fStripMisO.out fStripScratch.out fStripIn.out FSSR Status Report: Completion of the Functional Design Phase Hoff, J.R.; Mekkaoui, A.; Yarema, R.

(one for each time slice) Monte Carlo Data file 128 columns (one for each strip) 1 Time Slice = 1 FSSR Clock All Jim’s simulations assume 132ns FSSR Clock period! simulation with FSSR Clock = BCO Clock  1 Time Slice = 1 BCO Clock FSSR Clock = 4x BCO Clock  4 Time Slices = 1 BCO Clock in the Monte Carlo Data file 3 empty (i.e. all zero) buckets have been inserted between each bucket with hits in it 000001000 000000000 010000000 0000000000000 0000001000000 ………. (one for each time slice) # rows …… …… 000000000 000010000 0000100000000 0000000000011 0000000000000 ………. To avoid further misunderstanding in the following I will only talk about the FSSR Clock

Input Files File: FSSR2.v 2 interactions per beam crossing 2 interactions per beam crossing, but with a chip clock that is 4 times as fast as the beam crossing clock an alternate set of Monte Carlo simulations for 2 interactions per beam crossing The fStrip.XXX.dat files are just simple hit files to exercise the back end. They represent different hit probabilities.

Silicon Strip Detector Model Monte Carlo Data file has no timing information. It just answers the question: Was this strip hit this FSSR clock period? Turn on delay: models the combination of the pre-amp rise time and the discriminator firing delay Dead time: models the combination of the pre-amp fall time and the discriminator firing delay FSSR Clk MC Hits FSSR Hits Turn on delay Dead time 2nd Hit “lost” due to dead-time

The Report Efficiency = Line 4 / Line 1 File: fStripDat.out All the information needed for the evaluation of the chip efficiency are summarized in one txt file File: fStripDat.out Line1: Sum total of “Original Data” Line2: Sum total of “Recorded Data” Line3: Garbage Output Line4: The matches Line5: The missing “Original Data” Line2 + Line5 should equal Line1 Line6: Unmatched “Recorded Data” Line4 + Line6 should equal Line2 Efficiency = Line 4 / Line 1

Setting up the FSSR clock File: FSSR2.v SyncClk 9.4286 ns FSSRclk 132ns

Setting up the Master clocks File: FSSR2.v MClkA MClkB 3.57ns 3.57ns 3.57ns 3.57ns 14.28ns

Turn-on and dead-time setting File: StripConstans.v FSSR Clk MC Hits FSSR Hits 20ns 180ns Front-end can be modeled as: Turn-on time [ns] Dead time [ns] Slow 60 500 Fast 10 200 ns 20 180

State of the art I have got all the FSSR2 model files from Jim Hoff (FNAL) Simulation with Verilog-XL works fine: simulation terminates with all .out file correctly written Procedure to set the FSSR clock, Master clocks, Turn-on delay and dead time, number of output lines, almost fully understood Simulation results do not fully match data provided by Jim in the “FSSR Status Report” document… see next slide

Comparison of simulation results Jim Hoff simulation results My simulation results 0.4 % 0.8 % 1.3 % Occupancy @ FSSR clk = BCO Matched results Unmatched results (but I am not sure we are using exactly the same Monte Carlo Data files)… still working on it

FSSR2 efficiency Very preliminary results! FSSR Clock = 7.5 MHz Master Clock = 70 MHz Front-End Model= 200 ns # of output lines = 6 # of time slices = 5000 FSSR2 can handle 0.4% occupancy with efficiency > 99% At 3% occupancy the efficiency is about 88 %

Simulation for SuperB Layer1 FSSR2 must be tested with realistic data created by Monte Carlo analysis of the interaction region For the upcoming activity we need Monte Carlo Data files with the occupancy foreseen for SuperB Layer1 (7.5 % according to [*]) Evaluate the effect of the following parameters on the chip efficiency: FSSR clock Master Clocks Turn-on delay and the dead-time # of active output lines [*] Lorenzo Vitale Strip layers design: first considerations X SuperB General Meeting - SLAC - 07 October 2009

Conclusions Activity on FSSR2 verilog simulation successfully started Some training activity needed to better understand the whole functionality of the FSSR2 verilog model Upcoming activity will test the effect of FSSR clock, Master Clocks, turn-on delay, dead-time and # of active output lines on the chip efficiency Monte Carlo Data files with the occupancy foreseen for SuperB Layer1 are needed

Acknowledgments I would like to thank Jim Hoff for the constant support provided throughout this work

Spare slides

List of Files Input Files FSSR2 Model Output Files silhits_2int.dat silhits_2intx4.dat silhits_4intx4.dat silhits_6intx4.dat ……… fStrip.001.dat fStrip.002.dat fStrip.003.dat fStrip.01.dat fStrip.02.dat fStrip.03.dat FSSR2.v daq.v stripBlocks.v stripCell.v stripEOC.v stripCore.v stripDataInt.v stripProgInt.v stripConstants.v fStripDat.out fStripIn.out fStripOut.out fStripMatch.out fStripMis.out fStripMisO.out fStripScratch.out

FSSR Clock = 4 x BCO Clock File: silhits_2int.dat File: silhits_2int_bx4.dat FSSR Clock = BCO Clock FSSR Clock = 4 X BCO Clock

FSSR2 Efficiency Model fails at occupancy > 3 %

(one for each time slice) Occupancy 128 columns (one for each strip) Monte Carlo Data File 000001000 000000000 0000000000000 ………. …… …… (one for each time slice) # rows 000000000 000010000 0000100000000 0000000000011 0000000000000 ………. # events Occupancy [%] = · 100 # rows · 128