1. An FPGA Implementation of a Brushless DC Motor Speed Controller
Alecsa, B.; Onea, A.; Design and Technology in Electronic Packaging (SIITME), 2010 IEEE 16th International Symposium for Digital Object Identifier: /SIITME Publication Year: 2010 , Page(s):
指導教授:龔應時
學 生:林哲偉
學 號:M
PPT製作:100%

2. Outline Abstract INTRODUCTION BRUSHLESS DC MOTOR DRIVING
CONTROLLER DESIGN AND FPGA IMPLEMENTATION
CONCLUSION

3. Abstract In this paper, a low cost digital controller is presented.
For experimental testing, the controller is implemented inside a field programmable gate array (FPGA) device.
The developed design is validated in a modular fashion by logic simulation and experimental results are provided.
The main contribution is the resented controller design methodology for FPGA implementation.

4. INTRODUCTION
The brushless motors are becoming more and more widespread in the fields of industrial electronics, home appliances, automotive and robotics.
This is due to their higher efficiency and lower maintenance compared to conventional brushed DC motors.
In this paper, the focus is on the low cost Spartan-3E device, produced by Xilinx, Inc., and the possibilities it offers for controller implementation.
The device used in the experimental setup is an XC3S500E, which provides 20 embedded multipliers 18x18 bits wide [3].

5. BRUSHLESS DC MOTOR DRIVING(1/4)
BLDC motors are a type of synchronous motors: the magnetic field generated by the stator and the magnetic field generated by the rotor rotate at the same frequency.
BLDC motors can be built in single-phase, two-phase or three-phase configurations. The last type is the most widely used [4].
Typical back EMF waveforms for a three-phase BLDC motor with trapezoidal flux distribution are shown in Fig. 1.

6. BRUSHLESS DC MOTOR DRIVING(2/4)
Fig. 1. Typical three phase trapezoidal back EMF.

7. BRUSHLESS DC MOTOR DRIVING(3/4)
The typical inverter drive system for a BLDC is presented in Fig. 2.
Fig. 2. Three phase inverter bridge for BLDC driving..

8. BRUSHLESS DC MOTOR DRIVING(4/4)
Table 1 shows the typical correspondence between the Hall sensor code, the phase current direction and the switch state, for clockwise rotation of the BLDC motor.

9. CONTROLLER DESIGN AND FPGA IMPLEMENTATION(1/5)
Fig. 3 presents the block diagram of the controller. In the following sections, each part of the controller is explained.
Fig. 3. BLDC motor speed controller block diagram

10. CONTROLLER DESIGN AND FPGA IMPLEMENTATION(2/5)
A. Change Detection Logic
The Hall sensors state is saved in D type flip-flops (FF) at every clock signal rising edge. This synchronizes the inputs with the clock signal. A second layer of FFs is used to save the previous inputs value. Comparator logic between the first and the second FFs layers signals a change in the input state. This one clock cycle pulse is used by the dead band generation logic to start the dead time measurement.
B. Commutation Logic
Based on the commutation sequence presented in Table I, the commutation logic is designed. Additional to the Hall sensors reading, an active low validation input is used to delay the transistor command by a preset dead time. This prevents the over current through the driver during the state change of two transistors on the same side (high or low): the transistor that must turn off may be still on when the next transistor in sequence is already on, if the command is given simultaneously. This is why the on command must be delayed from the off command.

11. CONTROLLER DESIGN AND FPGA IMPLEMENTATION(3/5)
C. Dead Band Generation Logic
As discussed in the previous section, the commutation from one energizing state to another should be delayed by a so called “dead time” long enough to cover the transistor switch on/switch off time. For the experimental setup used in this case, a dead time of at least 0.5μs was required.

12. CONTROLLER DESIGN AND FPGA IMPLEMENTATION(4/5)
D. PWM Generation and Output Validation Logic
The PWM generation logic consists of a 16 bit counter and a D type FF, both with synchronous reset, and two 16 bit equality comparators. Both comparators have one input connected at the counter output. The counter is driven by the same 50MHz clock signal. The PWM period is set by the constant value (per_val) at the input of the first comparator. When the comparator detects that this value was reached by the counter, it will reset the counter and set the FF. The PWM duty cycle is set by the value at the input of the second comparator (dc_val). This value must be lower than per_val. When a match is detected between the counter output and the duty cycle value, the FF is reset. The output of the FF is therefore active for a limited amount of time, given by:
For the experimental setup, the PWM frequency was set to 20kHz by setting a per_val value of 2499:

13. CONTROLLER DESIGN AND FPGA IMPLEMENTATION(5/5)
E. Speed Estimation
The speed estimation logic consists of a 16 bit counter and edge detection logic for the QEP signals. For a better resolution of the speed estimation, both the rising and falling edges of the two QEP signals are counted.

14. CONCLUSION
This paper describes a method to implement a digital BLDC motor speed controller inside an FPGA device. The controller design is a classical PI type, but the implementation method is the novelty.
Using the embedded multipliers of the Spartan-3E FPGA device, the computation time for the control algorithm is reduced to only one clock cycle, taking less than 20ns.