1 A hardware description language is a computer language that is used to describe hardware. Two HDLs are widely used Verilog HDL VHDL (Very High Speed Integrated Circuit Hardware Description Language) Schematic design entry can be replaced by writing HDL code that CAD tools understand. CAD tools can verify the HDL codes, and create the circuits automatically from HDL codes.

2 VHDL represents another high level language for digital system design. In this course we study Verilog HDL reason: used more often in electronic and computer industry programming style is very similar to C programming language

3 We use Verilog, not VHDL, in EE 242. Verilog is more popular in industry than VHDL They offer similar features History of Verilog In 1980s, originally developed by Gateway Design Automation. In 1990, was put in public domain. In 1995, adopted as an IEEE standard In 2001, an enhanced version, Verilog 2001

4 Verilog HDL is for writing models of a system Reasons for modeling requirements specification documentation testing using simulation formal verification synthesis Goal most reliable design process, with minimum cost and time avoid design errors!

5 Design entry in several different ways Truth tables Schematic captures Hardware description languages (efficient !) Two types of representations in Verilog Structural Behavioral

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8 HDL model specifies the relationship between input signals and output signals HDL uses special constructs to describe hardware concurrency, parallel activity flow, time delays and waveforms Verilog code for a AND gate module and_gate(y, x1, x2); inputx1, x2; outputy; and(y, x1, x2); endmodule

9 Generally, HDLs have built-in gate-level primitives Verilog has NAND, NOR, AND, OR, XOR, XNOR, BUF, NOT, and some others The gates operate on input values producing an output value typical Verilog gate instantiation is: and #delay instance-name (out, in1, in2, in3, …); optional“many”

10 examples AND gate  and (y, x1, x2); OR gate  or (y, x1, x2, x3, x4); NOT gate  not (y, x); Keywords: and, or, not are reserved

11 Module A logic circuit  module Its ports: inputs and outputs Begins with module, ends with endmodule example wire g,k,h;

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14 One more example wire z1,z2,z3,z4;

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17 module mux (f, a, b, sel); outputf; inputa, b, sel; wire nsel,f1,f2; and #5g1 (f1, a, sel), and g2 (f2, b, sel); or #5g3 (f, f1, f2); notg4 (nsel, sel); endmodule a b f sel delay from a or b to f.

18 Why behavioral representation? Using primitives can be tedious when circuits are large It is desired to describe the circuit in more abstract level – behavior Two fundamental types of behavior model Logic expression Procedural statements CAD synthesis tools use this representation to construct the actual circuit

19 Logic expression continuous assignment

20 Procedural statements always block Sensitivity list: statements evaluated only when one or more signals in list changes value. Statements evaluated in order One or more statements in one always block One or more always blocks in a module Declare a signal as a variable reg if the signal is assigned a value by procedural statements

21 module m555 (clock); output clock; reg clock; initial #5 clock = 1; always #50 clock = ~ clock; endmodule One more example

22 White space characters are ignored : SPACE, TAB, new line, blank lines Two forms to introduce comments single line: begin with // multiple lines: /*…..long comments */ Verilog is case sensitive Lower case letters are unique from upper case letter All Verilog keywords are lower case Identifiers begin with an alphabetic character or the underscore character may contain alphabetic characters, numeric characters, _, and $ up to 1024 characters long. The instance of a module must be named while the instance name of a primitive is optional. `include “ *.v”

23 Comments Lower case key words identifiers