Agilent DVS Restricted September 21, 2006 Agenda Xilinx Spartan-3E FPGA Demo Guide FPGA Functional Debug Using LA Market Competitive

Agilent DVS Restricted September 21, 2006 Demo Requirements: Hardware –1680, 1690, 16800, Series software version or greater –Xilinx Spartan-3E demo board –USB cable (Standard Type A to Type B USB cable) Software –B4655A Xilinx FPGA dynamic probe application SW installed on Logic Analyzer –Xilinx.bit configuration file and.cdc naming files atc2_state_8mA.bit atc2_state.cdc Probing –Flying Leads

Agilent DVS Restricted September 21, 2006 Contents in the Demo Guide

Agilent DVS Restricted September 21, 2006 Altera FPGA Demo Quick Start 1.Download the updated B4656A Altera FPGA demo guide and files from the field portal debug/sales/#logic 2.To run the Xilinx Spartan-3E FPGA demo, first, you have to install the ‘B4655A Xilinx FPGA Dynamic Probe’ application software. 3.Install the USB driver to Logic Analyzer by following the ‘4. USB JTAG Driver Installation Guide’. 4.Now, you can start to demonstrate the Xilinx Spartan-3E FPGA demo by follow the demo guide either using a Flying lead set (see 6. Xilinx Spartan-3E FPGA Demo Guide).

Agilent DVS Restricted September 21, 2006 Demo Board Connections

Agilent DVS Restricted September 21, 2006 Demo Board Connections (Con’t) Xilinx Spartan-3E board pin location LA Pod Channel IO1Ch7 IO2Ch0 IO3Ch1 IO4Ch2 IO5Ch3 IO6Ch4 IO7Ch5 IO8Ch6 IO9Clk IO10Ch8 IO11Ch9 IO12Ch10 GND Gnd The demo contains of 4 Banks: i.Bank0 – 8-bit down counter + 3 signals from Button IO (BTN North, BTN East, BTN South) ii.Bank1 – 8-bit up counter + 3 signals from Switch IO (SW0, SW1, SW2) iii.Bank2 – Sine generation iv.Bank3 – Picoblaze address, 8KHz update

Agilent DVS Restricted September 21, 2006 Xilinx FPGA Dynamic Probe Demo 1.Setup your cable connection2.Configure your device (.bit) 3.Import your Bus and Signal (.cdc) 4.Click on the ‘Pin Mapping’ to set up the probe connected to the FPGA 7.Select your bank. 5.The system will proceed with the automatic pin mapping 8.The system is now set up to debug the FPGA design.

Agilent DVS Restricted September 21, 2006 Agenda Xilinx Spartan-3E FPGA Demo Guide FPGA Functional Debug Using LA Market Competitive

Agilent DVS Restricted September 21, 2006 Application Info / Target Buyer Functional test and debug for designs incorporating Xilinx or Altera FPGA technology … in the R&D department in a wide range of markets including … wireless (Nokia, Motorola, etc.), aerospace/ defense (Lockheed Martin, Raytheon, etc.), and computer (HP, Dell, etc). Key technical buyer is a system architect, FPGA designer or board designer

Agilent DVS Restricted September 21, 2006 The Old Way… Single pin example Connects to pod 3 channel 8 of the logic analyzer Goes to pin A2 of the mictor connector Pin C12 of the FPGA FPGAProbe footprint Logic Analyzer Pick internal signal and route to FPGA pin

Agilent DVS Restricted September 21, 2006 Manual Setup of Signal/Bus Names on Analyzer Determine which logic channel is connected to that pin Determine which connector pin it was routed to Look at schematic FPGAProbe footprint Logic Analyzer Hand type each name in LA for every signal routed to debug pins Signal name in FPGA Then, to change signals, Can take a few minutes to hours to recompile the design (plus risk of timing changes)

Agilent DVS Restricted September 21, 2006 Agilent FPGA Dynamic Probe Overview ATC2 Insert ATC2 core with Xilinx Core Inserter FPGA PC Board JTAG Control access to new signals via JTAG Parallel or USB Probe core output FPGA Dynamic Probe SW application supported by 1680/1690/16800/16900 Logic Analyzers or Mixed Signal Oscilloscopes

Agilent DVS Restricted September 21, 2006 Agilent Trace Core (ATC2) ATC2 Selection MUX Output to FPGA pins for debug Change signal bank selection from logic analyzer JTAG Select Up to 64 signal banks All banks have identical width (4 to 128 signals wide)

Agilent DVS Restricted September 21, 2006 Why An External Logic Analyzer (vs. Internal)? Provides a system level measurement -Inside the FPGA plus Outside the FPGA -Real time & Time correlated Doesn’t use internal FPGA Block RAM (needed by design) Easier to use, more powerful (triggering, memory depth, etc.) Xilinx and Altera both offer ILA (Internal Logic Analyzers) -Xilinx ChipScope PRO -Altera SignalTap -Main benefits: very low cost (no ext. HW), no device pins needed

Agilent DVS Restricted September 21, 2006 Agenda Xilinx Spartan-3E FPGA Demo Guide FPGA Functional Debug Using LA Market Competitive

Agilent DVS Restricted September 21, 2006 Top 3 Reasons “Why buy Agilent 16800/900 vs Tek TLA 5000/7000 for FPGA debug?” Value Proposition 1. Most Intuitive View of Target Activity 2. Simplest Process To Get Key Buses and Signals On Screen 3. Most Reliable Way To View Signals

Agilent DVS Restricted September 21, 2006 First Reason: “Why Buy Agilent for FPGA Debug?” “Why Buy Agilent?” Value Proposition Customer Needs/Problems Solved Agilent Features 1) Most Intuitive View of Target Activity See key state machines, address and data buses, and DSP data in basic bus format Automatic bus setup and display for each signal bank Agilent’s solution saves you more time and eliminates errors!

Agilent DVS Restricted September 21, ) Most Intuitive View of Target Activity “Why Buy?” Proof Points vs. Competitor Tek doesn’t offer bus definitions or setup with measurement core signal bank changes. They only display individual bits with updated names. If you want a bus view, set it up, totally manually. The integration of the FS2 FPGAView application with the TLA is very poor compared to Agilent’s solution.

Agilent DVS Restricted September 21, ) Most Intuitive View of Target Activity Demo of Proof Point Agilent:Buses defined, traces update automatically with bank switching No automatic bus definitions. Only see individual bits Bus set up manually – no name update with bank change!!! Tek/FS2:

Agilent DVS Restricted September 21, 2006 Tek Document “Simplifying Xilinx and Altera Debug” No bus names

Agilent DVS Restricted September 21, 2006 Second Reason “Why Buy Agilent for FPGA Debug?” “Why Buy Agilent?” Value Proposition Customer Needs/Problems Solved Agilent Features 2) Simplest Steps To View Signals Fewer, simpler steps from a single interface Automated threshold and bus setup One integrated application Connect, download, import signal names, auto pin-map, switch banks, buses and channels labeled and traces put to screen! All within Agilent’s LA GUI Agilent’s single-vendor solution is easier to purchase, use, and support!

Agilent DVS Restricted September 21, ) Simplest Steps To View Signals “Why Buy?” Proof Points vs. Competitor Tek’s solution requires 3 separate applications. Agilent took ½ the clicks to get a waveform. Change banks and look at bus: Agilent 4 clicks; Tek/FS2 ~ 22 clicks. See details: field.cos.agilent.com/fs2_clicks

Agilent DVS Restricted September 21, ) Simplest Steps to View Signals Demo of Proof Points Agilent – 5 easy steps, 1 User Interface Select Bank Automatic bus and channel setup

Agilent DVS Restricted September 21, ) Simplest Steps to View Signals Demo of Proof Points FS2 FPGAView to manually map pins, import signal names Tek LA to view “named” channels, must manually setup buses, thresholds, etc FS2 FPGAView to switch banks --- renames channels, leaves old data Three applications with Tek vs. one with Agilent! Altera Quartus Programmer to connect to cable and program FPGA

Agilent DVS Restricted September 21, 2006 Third Reason “Why Buy Agilent for FPGA Debug?” “Why Buy Agilent?” Value Proposition Customer Needs/Problems Solved Agilent Features 3) Most Reliable Way To View Signals Confidence that signals seen on screen are correct a) Automatic threshold setting and capture mode to match measurement core parameters b) Bank change clears data Agilent gives you confidence that the signals you’re seeing are correct!

Agilent DVS Restricted September 21, ) Most Reliable Way To View Signals “Why Buy?” Proof Points vs. Competitor Tek requires manual setting of thresholds and capture mode. Acquisition defaults to timing mode, even with state core. (For more see With bank change, Tek changes channel names but leaves old, irrelevant data!

Agilent DVS Restricted September 21, 2006 Most Reliable Way To View Signals Demo of Proof Point #1 Fastest validation/debug process Agilent: Capture mode, clocking, thresholds set to match measurement core Tek: Altera Logic Analyzer Interface (LAI) selected to create a State core Tek logic analyzer NOT set up to match core … comes up default in timing mode + Default Threshold s

Agilent DVS Restricted September 21, 2006 What about Xilinx FPGA support? ALL of the previous applies, PLUS it gets even better! … due to our Auto Pin Mapping (even faster time to get signals to screen and get your target debugged --- AND a more reliable capture) And 2X Time Division Multiplexing state core (requires ½ the FPGA pins for the same internal # of signals accessed)

Agilent DVS Restricted September 21, 2006 Tek Doesn’t Have Auto Pin Mapping Proof: Tek Document “Simplifying Xilinx and Altera Debug”, p. 9

Agilent DVS Restricted September 21, 2006 Proof: Tek Document “Simplifying Xilinx and Altera Debug”, p. 9 Tek Doesn’t Have Auto Pin Mapping

Agilent DVS Restricted September 21, 2006 Proof: Tek Document “Simplifying Xilinx and Altera Debug” p. 9 Tek Doesn’t Have 2X TDM Core

Agilent DVS Restricted September 21, 2006 Datasheets, FAQ, & Resource Calculator Options for Xilinx –With Logic Analyzers –With 8000 Series MSOs –With 6000 Series MSOs Options for Altera –With Logic Analyzerswww.agilent.com/find/FPGAwww.agilent.com/find/FPGA –With 8000 Series MSOs –With 6000 Series MSOs