1. Logic Analyzers EECS150 Fall2008 - Lab Lecture #5 Arjun Singh
Adopted from slides designed by Greg Gibeling
9/26/2008
EECS150 Lab Lecture #5

2. Today Lab #3 Solution Synplify Warnings Debugging Hardware
Administrative Info
Logic Analyzer
ChipScope
9/26/2008
EECS150 Lab Lecture #5

3. Lab #3 Solution (1) FSM.pdf Testbench Use this format for ALL FSMs!
It is concise
It will synthesize well
Everyone will be able to read it
Testbench
Thorough
Automated
A little complicated
9/26/2008
EECS150 Lab Lecture #5

4. Lab #3 Solution (2) module Lab3Testbench initial begin Reset = 1'b0;
Enter = 1'b0;
ResetCombo = 1'b0;
Code = 2'b00;
#(`Cycle);
Reset = 1'b1;
ResetCombo = 1'b1; …
9/26/2008
EECS150 Lab Lecture #5

5. Lab #3 Solution (3) for (CodeCounter = 0; CodeCounter < 5'h10;
CodeCounter = CodeCounter + 1) begin
end
Enter = 1'b1;
Code = CodeCounter[1:0];
#(`Cycle);
Code = CodeCounter[3:2];
Enter = 1'b0;
case ({Open, Error, Prog1, Prog2}) …
endcase
Reset = 1'b1;
#(`Cycle);
Reset = 1'b0;
9/26/2008
EECS150 Lab Lecture #5

6. Synplify Warnings (1) Why Bother? Incomplete Sensitivity List
Part of your project grade
Major warnings will cost points
Knowing these will make your life easier
Saves debugging
Incomplete Sensitivity List
ModelSim will use the sensitivity list
Synplify pretty ignores it
9/26/2008
EECS150 Lab Lecture #5

7. Synplify Warnings (2) input Clock; reg [31:0] Count; // Counter
(posedge Clock)
Count <= Count + 1;
OK!
input [15:0] A, B;
output [31:0] Sum;
output COut;
// Adder
( * )
{COut, Sum} = A + B;
input [15:0] A, B;
output [31:0] Sum;
output COut;
// Adder
(A)
{COut, Sum} = A + B;
OK!
9/26/2008
EECS150 Lab Lecture #5

8. Synplify Warnings (3) Latch Generated reg [1:0] CS, NS; wire A;
( * ) begin // Next state logic
NS = CS;
case (CS)
STATE_1: NS = STATE_2;
STATE_2:
if (A) NS = STATE_3;
STATE_3:
endcase
end
input [1:0] select;
input A, B, C;
output Out;
reg Out;
// Mux
(select or A or B or C) begin
case (select)
2’b00: Out = A;
2’b01: Out = B;
2’b10: Out = C;
9/26/2008
EECS150 Lab Lecture #5

9. Synplify Warnings (4) Combinational Loop
Must remove the loop or add a register
Synplify wont show you the loop
Comment out code till it goes away 1 3 2 1
∞??
∞?? 2 1
9/26/2008
EECS150 Lab Lecture #5

10. Synplify Warnings (5) FPGA_TOP2 always has warnings
Un-driven Input
Unconnected Output
These are truly unneeded pins
Things like the audio chips…
In your modules these are a problem
Synplify will optimize your design
Unconnected modules removed
9/26/2008
EECS150 Lab Lecture #5

11. Synplify Warnings (6) Why bother? Warnings are the only syntax check
Getting rid of warnings saves debugging
Synplify warnings will result in lost points
Warnings are the only syntax check
Verilog is a forgiving language
Undeclared variables default to 1 bit wires
This isn’t a good thing
9/26/2008
EECS150 Lab Lecture #5

12. Administrative Info Midterm 1 Next Tuesday: 9/30 Review Sessions
125 Cory, during lecture
DO NOT go to 306 Soda
Review Sessions
Saturday
7pm; 125 Cory
Monday
9/26/2008
EECS150 Lab Lecture #5

13. Debugging Hardware (1) Using the logic analyzer / ChipScope
The most reliable tool you have
When used properly
Use the triggers effectively
Trigger on recurring sequences
Trigger on errors
An unstable display is useless
Compare synthesis to simulation
ChipScope is almost as good as simulation
9/26/2008
EECS150 Lab Lecture #5

14. Lab #5: Logic Analysis (1)
Logic Analyzer
HP54645D Mixed Signal Oscilloscope
Analog Oscilloscope
Digital Logic Analyzer
Graphs Signals vs Time
Like a timing diagram
Invaluable for Debugging
This is your only tool for examining your clocks
Easy to see trends in signals…
9/26/2008
EECS150 Lab Lecture #5

15. Lab #5: Logic Analysis (2)
Exhaustive FSM Testing
Very similar to Part3 of Lab #4
You’ll be mapping the whole FSM
No bubble-and-arc to start from
No single step
Takes an input every cycle at 27MHz
Much too fast to see on the LEDs
Logic Analyzer!
9/26/2008
EECS150 Lab Lecture #5

16. Lab #5: Logic Analysis (3)
9/26/2008
EECS150 Lab Lecture #5

17. Lab #5: Logic Analysis (4)
Procedure
Set up the Logic Analyzer
Synthesize the design
Write a test pattern and set SW10
Press Single on the logic analyzer
Press Reset to start the test
Examine the waveforms
Build a bubble-and-arc diagram
9/26/2008
EECS150 Lab Lecture #5

18. The Logic Analyzer (1) Graphs Voltage vs Time
Takes real signals from a CUT
Can show both analog and digital signals
Great for signal quality, delay, timing
9/26/2008
EECS150 Lab Lecture #5

19. The Logic Analyzer (2) 16 Digital Inputs Excellent Debugging Tool
Not very many signals (Wait till next week)
Trigger Controls
Digital Controls
9/26/2008
EECS150 Lab Lecture #5

20. The Logic Analyzer (3) Read the Lab This is just a quick 10min intro
Please ask questions
9/26/2008
EECS150 Lab Lecture #5

21. ChipScope (1) Software based logic analyzer
Get results on the computer
Put a logic analyzer right into the FPGA
ICON – Connects FPGA to software
ILA – Does the actual analysis
More flexible than the bench analyzers
But not as timing accurate
9/26/2008
EECS150 Lab Lecture #5

22. ChipScope (2) Steps to use ChipScope Generate an ICON Generate an ILA
Connect the ILA to the ICON
Synthesize, and implement your design
With the ILA and ICON
Program the CaLinx board
Run the ChipScope Pro Analyzer
Runs over the JTAG not Slave Serial
9/26/2008
EECS150 Lab Lecture #5

23. ChipScope (3) Logic Analyzer Similarities/Differences
Triggering is similar
Can be set to show waves before trigger
Can trigger on repeated or combined events
Data/Trigger can be MUCH bigger
Up to 256bits wide
As many samples as Block RAM on the FPGA
Data is captured synchronously
Can’t look at clocks
Much easier to view waveforms
9/26/2008
EECS150 Lab Lecture #5

24. ChipScope (4) You will NEED ChipScope
You cannot debug a large design without it
Bench analyzers wont show enough signals
9/26/2008
EECS150 Lab Lecture #5

25. ChipScope (5) Now for a 10 min demo… Generate ICON Generate ILA
Instantiate in Verilog
Synthesize design
View waveforms in ChipScope wave window
9/26/2008
EECS150 Lab Lecture #5