T. Gorski, et al., U. Wisconsin, April 28, 2010 SHLC RCT MicroTCA Development - 1 SLHC Cal Trigger Upgrade SLHC Regional Calorimeter Trigger MicroTCA Development Work T. Gorski, P. Klabbers University of Wisconsin April 28, 2010

T. Gorski, et al., U. Wisconsin, April 28, 2010 SHLC RCT MicroTCA Development - 2 MicroTCA Prototype Crate uBlade Puma 600W Power Supply NAT MCH ELMA Enclosure and Backplane

T. Gorski, et al., U. Wisconsin, April 28, 2010 SHLC RCT MicroTCA Development - 3 System R&D: RCT FPGA Firmware Environment Block Diagram Controller Mezzanine Card (CMC) BASE-X Ethernet to Fabric A (SLHC RCT Board) FPGA Flash (Xilinx FPGA) TTC & Trigger Pipeline(HDL) High Speed Links carrying Trigger Data, Clocks (Backplane and Front Panel) MAC Core Microblaze Processor (Firmware Core) Trigger I/O Interface (HDL) Processor Local Bus (PLB) Interface Simple Asynch. Interface ( Parallel I/O To other On-Board FPGAs) SDRAM Ctrllr IPMI Config (SPI) MODULE POWER Pwr Ctl & Monitoring

T. Gorski, et al., U. Wisconsin, April 28, 2010 SHLC RCT MicroTCA Development - 4 Ethernet R&D: BASE-X Ethernet Development Platform (MicroTCA std) SATA cable running 1000BASE-X Ethernet Virtex-5 FPGAs running Echo server and client under Xilkernel and TCP/IP stack on two modified ML506 evaluation boards Performance: Running TCP/IP Stack under Xilkernel— XMT: 4-40 Mbps (traffic) RCV: Mbps

T. Gorski, et al., U. Wisconsin, April 28, 2010 SHLC RCT MicroTCA Development - 5 Prototype Card Development (Both Boards in PCB Fab Stage) Controller Mezzanine Card (CMC) Rev A AVR32 Microcontroller IPMI Interface to MicroTCA System uTCA-SATA Test Card Base-X Ethernet test bed CMC Test Carrier

T. Gorski, et al., U. Wisconsin, April 28, 2010 SHLC RCT MicroTCA Development - 6 Ethernet R&D: Initial MicroTCA BASE-X Ethernet Test (May/June 2010) ELMA MicroTCA Backplane NAT MCH (BASE-X Switch) BaseT Switch ML506 Board (SATA Cable) (SATA to Fabric A Test Board) (1000BASE-X Ethernet on UTCA Fabric A) (Iperf server runs on FPGA) PC (Running Iperf Client) (CAT-5 Cable) (Network Uplink)

T. Gorski, et al., U. Wisconsin, April 28, 2010 SHLC RCT MicroTCA Development - 7 Hardware/Software R&D: Controller Mezzanine Card (CMC) 55mm x 45 mm module 84-pin PMC connector to AMC module Stands 10mm above main board Services IPMI function for module Geographical Address Main module 12V power control Passes IP address info from IPMI to FPGA Controls boot mode of FPGA via CPLD on main board Based on Atmel UC3A1 AVR32 Microcontroller Runs off of the +3.3V MicroTCA Management Power Software Development (C code in AVR FLASH) during Summer 2010 Use uTCA-SATA Test Card as a Mezzanine Carrier

T. Gorski, et al., U. Wisconsin, April 28, 2010 SHLC RCT MicroTCA Development - 8 Trigger Algorithm R&D: 2x2 Firmware Test Bed 4 Aux Cards in a 2x2 test fabric TTC-based timing and link synchronization test bed Prototype Test Bed for Rocket I/O “Channel Bonding” for latency management For Testing Trigger Algorithms with Data Sharing C source code for test pattern generation RS-232 Hyperterminal interface

T. Gorski, et al., U. Wisconsin, April 28, 2010 SHLC RCT MicroTCA Development - 9 Trigger Algorithm R&D: 2x2 Firmware Test Bed Fabric MHz OSC To BPCK1, Slots 0-3 4X (Passive) 4X 3X 4x4 Switches 4X Ch 14 & 15, CK2->CK3 (TTC) Input Card Level Processing Card Level

T. Gorski, et al., U. Wisconsin, April 28, 2010 SHLC RCT MicroTCA Development - 10 SLHC RCT MicroTCA Activity Summary 10-Slot MicroTCA Crate now in lab CMC and uTCA-SATA test boards in PCB fabrication For building IPMI and embedded Base-X Ethernet capabilities into MicroTCA boards Learning how NAT-MCH supports these functions Developing expertise writing TCP/IP server applications to run in FPGA (e.g., HAL, JTAG) 2x2 Test Fabric constructed using 4 Aux cards and a test fixture PCB System synchronization and link data alignment work—Channel Bonding Test bed for multi-FGPA Trigger Algorithm firmware development Lessons learned in near-term activities to be put to work on SLHC RCT Trigger Prototype boards later in 2010