CS1103 Arunima Shukla 130420111007 Asim Marchant 130420111008 Urja Kantharia 130420111030 Harsh kosambia 130420111033 Digital Electronics Mini Project.

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Presentation transcript:

CS1103 Arunima Shukla Asim Marchant Urja Kantharia Harsh kosambia Digital Electronics Mini Project

 Sequential Logic Latches & Flip-flops 1. Introduction Flip-flops Flip-flops :  S-R Flip-flop S-R Flip-flop  D Flip-flop D Flip-flop  J-K Flip-flop J-K Flip-flop  T Flip-flop T Flip-flop

 Introduction  A sequential circuit consists of a feedback path, and employs some memory elements. Combinational logic Memory elements Combinational outputs Memory outputs External inputs Sequential circuit = Combinational logic + Memory Elements

 Introduction  There are two types of sequential circuits:  Synchronous: outputs change only at specific time  Asynchronous: outputs change at any time  Bistable logic devices: latches and flip-flops.  Latches and flip-flops differ in the method used for changing their state.

 S-R Latch  Complementary outputs: Q and Q'.  When Q is HIGH, the latch is in SET state.  When Q is LOW, the latch is in RESET state.  For active-HIGH input S-R latch : R=HIGH (and S=LOW)  RESET state S=HIGH (and R=LOW)  SET state both inputs LOW  no change both inputs HIGH  Q and Q' both LOW (invalid)!

 S-R Latch  For active-LOW input S'-R' latch (also known as NAND gate latch), R'=LOW (and S'=HIGH)  RESET state S'=LOW (and R'=HIGH)  SET state both inputs HIGH  no change both inputs LOW  Q and Q' both HIGH (invalid)!

 S-R Latch  Characteristics table for active-high input S-R latch: Characteristics table for active-low input S'-R' latch: SRSR Q Q' SRSR Q Q'

 D Flip-flop  D flip-flop: single input D (data)  D=HIGH  SET state  D=LOW  RESET state  Q follows D at the clock edge.  Convert S-R flip-flop into a D flip-flop: add an inverter. A positive edge-triggered D flip-flop formed with an S-R flip-flop. S C R Q Q' CLK D  = clock transition LOW to HIGH

 J-K Flip-flop  J-K flip-flop: Q and Q' are fed back to the pulse-steering NAND gates.  No invalid state.  Include a toggle state.  J=HIGH (and K=LOW)  SET state  K=HIGH (and J=LOW)  RESET state  both inputs LOW  no change  both inputs HIGH  toggle

 J-K Flip-flop  J-K flip flop : J Q Q' CLK Pulse transition detector K

 T Flip-flop  T flip-flop: single-input version of the J-K flip flop, formed by tying both inputs together.  Characteristic table. Q(t+1) = T.Q' + T'.Q T Q Q' CLK Pulse transition detector J C K Q Q' CLK T

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