FIGURE 4.1 SOC System Overview.

FIGURE 4.2 Memory Map Representation for an Intel Platform.

FIGURE 4.3 Basic Interrupt Controller Functions.

FIGURE 4.4 Interrupt Acknowledgment and Priority Schemes.

FIGURE 4.5 Cascaded 8259 Interrupt Controllers.

FIGURE 4.6 Local and I/O APIC Layout.

FIGURE 4.7 Local APIC Details.

FIGURE 4.8 LVT Local Interrupt Register Definition

FIGURE 4.9 I/O APIC Redirection Table Entry.

FIGURE 4.10 Interrupt Controller Hierarchy.

FIGURE 4.11 Logical Timer Configuration.

FIGURE 4.12 Increased Performance through Pipelining.

FIGURE 4.13 DDR Overview.

FIGURE 4.14 NAND Device Representation.

FIGURE 4.15 PCIe Physical Hierarchy.

FIGURE 4.16 PCI Configuration Header.

FIGURE 4.17 USB Hierarchy Examples.

FIGURE 4.18 Transaction Phases for USB Transfer to and from a Device.

FIGURE 4.19 Software Stack on ECHI Controller.

FIGURE 4.20 EHCI Register Classification. Source:

FIGURE 4.21 Async List Address, Head Queues, and Payload Description. Source: EHCI Intel Spec.

FIGURE 4.22 Single Master I 2 C Bus.

FIGURE 4.23 SPI Interface to Flash Parts.

FIGURE 4.24 Bluetooth Protocol Stack.

FIGURE 4.25 GPIO Read Pin Example.