VADA Lab.SungKyunKwan Univ. 1 Lower Power Design Overview 성균관대학교 조 준 동 교수

VADA Lab.SungKyunKwan Univ. 2 Motivation Portable Mobile (=ubiquitous =nomadic) Systems with limited for heat sinks Lowering power with fixed performance: DSPs in modems and cellular phones Reliability: Increasing power ! increasing electromigration, 40- year reliability guarantee (product life cycle of telecommunication industries) Adding fans to reduce power cause reliability to plummet. Higher power leads to higher packaging costs: 2-watt package can be four times greater than a 1-watt package Myriad Constraints: timing, power, testability, area, packaging, time-to-market. Ad-Hoc Design: Lack a systematic process leading to universal applicability.

VADA Lab.SungKyunKwan Univ. 3 Motivation for low-power/low- voltage IC design

VADA Lab.SungKyunKwan Univ. 4

VADA Lab.SungKyunKwan Univ. 5 Technological evolution and performance progress of Intel's micro processors

VADA Lab.SungKyunKwan Univ. 6 Power Dissipation in VLSI’s MPU1 clock memory I/O clock I/O logic memory MPU1ASSP1 ASSP2 MPU1: low-end microprocessor for embedded use MPU2: high-end CPU with large amount of cache ASSP1: MPEG2 decoder ASSP2: ATM switch

VADA Lab.SungKyunKwan Univ. 7 System Requirement Low-power, high-performance System –flexibility –low-power –high throughput Design consideration –programmable DSP meet the flexibility needed in various forms of computing –dedicated(vertically integrated) high throughput and low-power applications

VADA Lab.SungKyunKwan Univ. 8 DSP trends –[1]Dedicated or application-specific fixed(or hard-wired) 0.5um CMOS, mm 2 /MOP, 0.02mW/MOP –[2]Application-specific(programmable)DSP 10 times area, 25 times power than [1] –[3]General-purpose DSP more flexible and faster time to market 0.1mm 2 /MOP, 2mW/MOP assembly code rather than microcode by [2] –[4] General-purpose microprocessor high-level language 1mm 2 /MOP, 50mW/MOP

VADA Lab.SungKyunKwan Univ. 9 Current Design Issues in Lower Power Problem Energy-hungry Function by Network Server Infopad (univ. of California, Berkeley), weight < 1 pound, 0.5W (re ective color display) + 0.5W (computation,communication, I/O support) = 1W (Alpha chip: 25W StrongARM: 215 MHz at 2.0V:0.3W)runtime 50 hours, target: 100MIPS/mW. Deep-sub micron ( ) with low voltage for portable full motion video terminal; 0:5  m : 40 AA NiMH; 1  m : 1 AA NiMH System-On-A-Chip to reduce external Interconnection Capacitances Power Management: shut down idle units Power Optimization Techniques in Software, Architecture,Logic/Circuit, Layout Phases to reduce operations, frequency, capacitance, switching activity with maintaining the same throughput.

VADA Lab.SungKyunKwan Univ. 10 Road-Map in Semiconductor Device Complexity

VADA Lab.SungKyunKwan Univ. 11 V dd vs Delay use architecture optimization to compensate for slower operation, e.g., Parallel Processing and Pipelining for concurrent increasing and critical path reducing. Scale down device sizes to compensate for delay (Interconnects do not scale proportionately and can become dominant)

VADA Lab.SungKyunKwan Univ. 12 Good Design Methodologies

VADA Lab.SungKyunKwan Univ. 13 Synthesis and Optimization Pareto point

VADA Lab.SungKyunKwan Univ. 14 Low-power design techniques at different levels of abstraction

VADA Lab.SungKyunKwan Univ. 15 Low-Power Design Flow developed at LIS

VADA Lab.SungKyunKwan Univ. 16 Low Power Design Flow I

VADA Lab.SungKyunKwan Univ. 17 Low Power Design Flow II

VADA Lab.SungKyunKwan Univ. 18 Execution unit idle time(PowerPC 603)

VADA Lab.SungKyunKwan Univ. 19 System Integration

VADA Lab.SungKyunKwan Univ. 20 Reducing Waste Locality of reference Demand-driven / Data-driven computation Application-specific processing Preservation of data correlations Distributed processing

VADA Lab.SungKyunKwan Univ. 21 Energy-Efficient Design 1) Reduce the supply voltage  Energy of switching drops quadratically with the supply voltage  This drop is accompanied by reduced circuit speed 2) Minimizing switching capacitance  Exploiting locality of reference with distributed computational structures, minimizing global interactions  Enforcing a demand-driven policy that eliminates switching activities in unused modules  Preserving temporal correlation in data streams by minimizing the degree of hardware sharing

VADA Lab.SungKyunKwan Univ. 22 Switching Activity

VADA Lab.SungKyunKwan Univ. 23 Eliminating Redundant Computations

VADA Lab.SungKyunKwan Univ. 24 Power saving concepts ý Work with parallel computation and low frequency. ý Reduce pipe stages to save registers (try to avoid hazards). ý Disable input toggling when the block is at idle state. ý Work with minimum gate size to reduce the toggle current. ý For outputs with large fanout’s speed up the transition to reduce the short circuit current (invest toggle current in order to save short circuit current).

VADA Lab.SungKyunKwan Univ. 25 Low-power embedded system design low-power embedded applications: PDAs, mobile phones, etc. power-efficient processor cores(ARM) cache/memory organization for low power power management on embedded system chips, comparative analysis of power drawn by subsystems (CPU, hard disk, display, and standby) of notebooks

VADA Lab.SungKyunKwan Univ. 26 High level optimization for low power use of parallel and/or pipelined structures, the choice of data representations, the exploitation of signal correlations, the synchronization of signals for glitching minimization, and an accurate analysis of the shared resources. At the algorithmic-level, applying arithmetic and logic transformations to the block diagram

VADA Lab.SungKyunKwan Univ. 27 VLSI Signal Processing Design Methodology pipelining, parallel processing, retiming, folding, unfolding, look-ahead, relaxed look-ahead, and approximate filtering bit-serial, bit-parallel and digit-serial architectures, carry save architecture redundant and residue systems Viterbi decoder, motion compensation, 2D- filtering, and data transmission systems

VADA Lab.SungKyunKwan Univ. 28 Power-hungry Applications Signal Compression: HDTV Standard, ADPCM, Vector Quantization, H.263, 2-D motion estimation, MPEG-2 storage management Digital Communications: Shaping Filters, Equalizers, Viterbi decoders, Reed- Solomon decoders

VADA Lab.SungKyunKwan Univ. 29 Power Estimation Techniques Circuit Simulation (SPICE): a set of input vectors, accurate, memory and time constraints Monte Carlo: randomly generated input patterns, normal distributed power per time interval T using a simulator switch level simulation (IRSIM): defined as no. of rising and falling transitions over total number of inputs Powermill (transistor level): steady-state transitions, hazards and glitches, transient short circuit current and leakage current; measures current density and voltage drop in the power net and identifies reliability problem caused by EM failures, ground bounce and excessive voltage drops. DesignPower (Synopsys): simulation-based analysis is within 8-15% of SPICE in terms of percentage difference (Probability-based analysis is within 15-20% of SPICE).

VADA Lab.SungKyunKwan Univ. 30 Power Estimation Techniques Static (non-Simulative) - useful for synthesis and architectural exploration –Probability-based –Entropy-based Dynamic (simulative) - useful for final power –Direct –Sampling-based –Compaction-based Hybrid (high-level simulation + low-level analytical model evaluation) –Power macromodels for datapath, control, memory –Instruction-level models for microprocessors, DSPs