1 load [2], [9] Transfer contents of memory location 9 to memory location 2. Illegal instruction

2 Review

3 CS501 Advanced Computer Architecture Lecture 31 Dr.Noor Muhammad Sheikh

4 load r1, [9] store r1, [2]

5 out [6], datap illegal instruction

6 load r1, [6] out r1, datap

7 I/O interface architecture for a DMA device Memory address Count Control DMA sequencer Bus control I/O address decode Packing, unpacking and buffering address Read, write Complete Bus request Bus grant Data Device control Device data

8 DMA Protocol 1. The CPU sets up DMA by providing device addresses, type of operation (R/W), memory addresses and the number of bytes to be transferred.

9 DMA Protocol 2. The DMA starts operation by getting control of the bus, transfers the data when available and generates next addresses until the transfer is complete.

10 DMA Protocol A number of controllers may be connected to one bus.

11 Buffer in DMA may provide flexibility to deal with delays in transfer or waiting

12 3. Once DMA transfer is complete, controller interrupts the processor which then determines if the entire operation is completed successfully and becomes the bus master DMA Protocol

13 Single-bus detached DMA CPU DMA module I/O Memory …

14 Single-bus, Integrated DMA-I/O CPU DMA module DMA module Memory I/O

15 I/O bus CPU DMA module Memory I/O … I/O bus System bus

16 DMA An I/O device transfers data at a rate of 10MB/s over a 100MB/s bus. The data is transferred in 4KB blocks. If the processor operates at 500MHz, and it takes a total of 5000 cycles to handle each DMA request, find the fraction of CPU time handling the data transfer with and without DMA

17 Solution Without DMA The processor here copies the data into memory as it is sent over the bus. Since the I/O device sends data at a rate of 10MB/s over the 100MB/s bus, 10 % of each second is spent transferring data.Thus 10% of the CPU time is spent copying data to memory

18 Solution With DMA time required in handling each DMA request is 5000 cycles. Since 2500 DMA requests are issued (10MB/4KB) the total time taken is 12,500,000 cycles. As the CPU clock is 500MHZ, the fraction of CPU time spent is 12,500,000/(500x10 6) or 2.5%.

19 Example A hard drive with a maximum transfer rate of 1MB/s is connected to a 32-bit, 10 MIPS CPU operating at a clock frequency of 100 MHz.Assume that the I/O interface is DMA based and it takes 500 clock cycles for the CPU to set- up the DMA controller. Also assume that the interrupt handling process at the end of the DMA transfer takes an additional 300 CPU clock cycles. If the data transfer is done using 2 KB blocks, calculate the percentage of the CPU time consumed in handling the hard drive.

20 Solution Since the hard drive transfers at the rate of 1MB/s, and each block size is 2KB, there are 1000/2=500 blocks transferred/ second Every DMA transfer uses =800 CPU cycles. This gives us 800x500=400,000=400x10 3 cycles/s For the 100 MHz CPU, this corresponds to (400x10 3 )/(100x10 6 )=4x10 -3 =0.4%

21 Cycle Stealing The DMA module takes control of the bus to transfer data to and from memory. it can either use the bus while the CPU is not using it. or it can force the CPU to temporarily suspend its operation. The latter approach is called cycle stealing

22 DMA and Interrupt breakpoints during an instruction cycle Instruction cycle Fetch Instruction Decode Instruction Fetch Operand Execute Instruction Store Result Process Interrupt Processor Cycle Processor Cycle Processor Cycle Processor Cycle Processor Cycle Processor Cycle DMA Breakpoints Interrupt Breakpoint

23 1. Microprocessor controlled device 2. Programmed I/O 3. Interrupt driven I/O 4. DMA

24 I/O Channel Architecture (a) Selector Selector Channel I/O Controller I/O Controller Control Signal Path to CPU Data and address Channel To main memory

25 Multiplexor Channel I/O Controller To CPU To memory (b) Mutiplexor

26 Selector channel A selector channel controls multiple high speed device. However, it is dedicated to a single device at a time. Every device is handled by a controller, or I/O module.

27 Multiplexor channel It can handle I/O with multiple devices at the same time. Byte multiplexor accepts or transmits characters to multilple devices. Block multiplexor interleaves blocks of data from several devices

28 DMA and memory systems DMA unit need to translate virtual address to physical address A transfer cannot easily cross a page boundary The DMA unit contains mappings from virtual to physical address The Operating system provides a mapping Mechanism initiated by the I/O Using this mapping the DMA unit need not worry about the location of virtual pages involved in the transfer

29 DMA and memory systems Break up the DMA transfer into a series of transfers All transfers stay within a single physical page I/O processor handles the ‘chained together’ transfers The operating system individually request each transfer

30 Coherency Solution 1. Route the I/O activity through the cache Ensures cache consistency Expensive Negative performance impact

31 Coherency Solution 2. Cache Flushing Selective invalidation Forced write back No hardware drawback More efficient in software

32 Coherency Solution 3.Hardware flushing Selective flushing through hardware