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Cis303a_chapt06_exam.ppt CIS303A: System Architecture Exam - Chapter 6 Name: __________________ Date: _______________ 1. What connects the CPU with other.

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Presentation on theme: "Cis303a_chapt06_exam.ppt CIS303A: System Architecture Exam - Chapter 6 Name: __________________ Date: _______________ 1. What connects the CPU with other."— Presentation transcript:

1 Cis303a_chapt06_exam.ppt CIS303A: System Architecture Exam - Chapter 6 Name: __________________ Date: _______________ 1. What connects the CPU with other devices and peripherals of the computer system? _________________________ 2. The primary bus of the computer consists of what elements? _________________________ 3. What is the amount of data that can be transferred across the system bus in one second if the data transfer unit is 32 bits and the CPU clock is 400 MHz? (show computations) 4. The bus clock is carried along what hardware device? _________________________ 5. Manners, etiquette, code of behavior, practice, set of rules, modus operandi, and method are also known as _________________________ 6. Devices other than the CPU and Primary Storage are called ______________ ______________ 1. System Bus 10 2. Data bus 10 2. Address bus 10 2. Control bus 10 3. 10 4. Control bus 10 5. Protocol 10 6. Peripheral devices 10 32 bits = 4 bytes 4 x 400,000,000 = 1,600,000,000 1.6 billion bytes per second 1.6 Giga Bytes

2 Cis303a_chapt06_exam.ppt CIS303A: System Architecture Exam - Chapter 6 7. Between a bus master and a bus slave, which one controls the actions on the bus? _________________________ 8. What controller handles transfer of information between I/O devices and memory. It frees up the CPU from having to control the bus data movement. _________________________ 9. With a CPU clock of 150 MHz, what is the bus cycle time? _________________________ 10. The system bus is an electronic element, give two (2) reasons that keep the speed of the bus from running at maximum. _________________________ 11. Name two (2) things that bus protocol governs _________________________ 7. Bus master 10 8. DMA 10 Direct Memory Access controller 9..000000006666 10 6.66 nanoseconds 10. 10 10 a) Noise b) Interference c) Time required for peripheral device interface circuits to set up --------------------------- 11.10 10 Transmitting/receiving format Content of information Timing (along with the system clock) Data Memory addresses Control messages 1 second / 150,000,000 220

3 Cis303a_chapt06_exam.ppt CIS303A: System Architecture Exam - Chapter 6 12. What is a communications pathway from the computer to a peripheral called? _________________________ 13. What connects an I/O device to the system bus and monitors the bus control lines? _________________________ 14. What is a standard bus designed for secondary storage devices called? It is a totally separate bus from the system bus. _________________________ 15.What is the name of a signal from an I/O device that is used to gain the attention of the CPU? _________________________ 16. What is a mechanism that allows a program to resume execution in exactly the same state (swapping registers)? _________________________ 17. What temporarily stores a small amount of data in memory? _________________________ 18. What acts like a buffer but the data is not necessarily temporary and also requires intelligent management? _________________________ 12. I/O Port 10 13. Device controller 10 14. SCSI 10 Small computer system interface 15. Interrupt 10 16. Stack processing 10 17. Buffer 18. cache


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