Temperature Aware Circuits A Temperature Sensor in the Interconnect Layer Matthew Lindsey

Outline Background Modeling the Interconnect –Technology Nodes –Optimal Sizes Temperature Sensor Circuit Conclusions

Background Current interconnect design falls short –Self-heating and electromigration both temperature dependent No current technique to measure temperature in the interconnect Mostly based on Banerjee’s work

The Interconnect Distributed model –Physical parameters from ITRS –Circuit parameters from PTM Optimal size (length and buffer size) –Performance Planning by Otten and Brayton

Optimal Size Node: 90nm Lcrit (um) SoptRout (Ohms) Rline (Ohms) M intermed global

Self Consistent Equation From Banerjee r: duty cycle ton/T Tm: new metal temperature

70nm: Global Interconnect Layer

The Sensor Modified ring oscillator circuit

Comparison 100C to 500C 90nm, global interconnect layer, using 150um length of wire

Conclusions Simulations Performed –130nm, 90nm, 70nm, for metal 1, intermediate and global interconnect for 100C to 500C in steps of 50C Found Temperature Sensor will be Effective in those Simulations Time Constraints Prevented Interconnect Model and Circuit Together in Same Simulation

Questions