MOSFET #5 OUTLINE The MOSFET: Sub-threshold leakage current Gate-length scaling Velocity saturation

Sub-Threshold Leakage Current We had previously assumed that there is no channel current when VGS < VT. This is incorrect. If fS > fF, there is some inversion charge at the surface, which gives rise to sub-threshold current flowing between the source and drain:

Sub-Threshold Slope S

How to minimize S?

MOSFET Scaling MOSFETs have scaled in size over time Reasons: Speed 1970’s: ~ 10 mm Today: ~50 nm Reasons: Speed Density

Benefit of Transistor Scaling IDS  as L  (decreased effective “R”) Gate area  as L  (decreased load “C”) Therefore, RC  (implies faster switch)

Circuit Example – CMOS Inverter

td is reduced by increasing IDsat

Constant-Field Scaling Voltages and MOSFET dimensions are scaled by the same factor k>1, so that the electric field remains unchanged

Constant-Field Scaling (cont.) Circuit speed improves by k Power dissipation per function is reduced by k2

VT Design Trade-Off Low VT is desirable for high ON current: IDsat  (VDD - VT) 1 <  < 2 But high VT is needed for low OFF current: log IDS Low VT VT cannot be scaled aggressively! High VT IOFF,low VT IOFF,high VT VGS

Since VT cannot be scaled down aggressively, the power-supply voltage (VDD) has not been scaled down in proportion to the MOSFET channel length

Generalized Scaling Electric field intensity increases by a factor a>1 Nbody must be scaled up by a to control short-channel effects Reliability and power density are issues

CMOS Scaling and the Power Crisis Active Power Density 1E+02 1E+01 1E+00 Power (W/cm2) 1E-01 1E-02 Passive Power Density 1E-03 1E-04 1E-05 0.01 0.1 1 Gate Length (μm) Lg/VDD/VT trends  increases in: Active Power Density (VDD2) ~1.3X/generation Passive Power Density (VDD) ~3X/generation Gate Leakage Power Density >4X/generation Source: B. Meyerson, IBM, Semico Conf., January 2004

esat is the electric field at velocity saturation: Velocity saturation limits IDSsat in modern MOSFETS Simple model: esat is the electric field at velocity saturation: for e < e sat for e  esat

MOSFET I-V with Velocity Saturation In the linear region:

Drain Saturation Voltage VDSsat If esatL >> VGS-VT then the MOSFET is considered “long-channel”. This condition can be satisfied when L is large, or VGS is close to VT

EXAMPLE: Drain Saturation Voltage Question: For VGS = 1.8 V, find the VDSsat of an NFET with Toxe = 3 nm, VT = 0.25 V, and WT = 45 nm, if L = (a) 10 mm, (b) 1 um, (c) 0.1 mm, and (d) 0.05 mm Solution: From VGS , VT, and Toxe , mn is 200 cm2V-1s-1. esat= 2vsat / mn = 8 104 V/cm m = 1 + 3Toxe/WT = 1.2

(a) L = 10 mm: VDSsat= (1/1.3V + 1/80V)-1 = 1.3 V (b) L = 1 mm: VDSsat= (1/1.3V + 1/8V)-1 = 1.1 V (c) L = 0.1 mm: VDSsat= (1/1.3V + 1/.8V)-1 = 0.5 V (d) L = 0.05 mm: VDSsat= (1/1.3V + 1/.4V)-1 = 0.3 V

IDSsat with Velocity Saturation Substituting VDSsat for VDS in the linear-region IDS eq’n. gives: For very short channel length: IDSsat is proportional to VGS–VT rather than (VGS – VT)2 IDSsat is not dependent on L

Short- vs. Long-Channel MOSFET Short-channel MOSFET: IDsat is proportional to VGS-VTn rather than (VGS-VTn)2 VDsat is lower than for long-channel MOSFET Channel-length modulation is apparent

Velocity Overshoot When L is comparable to or less than the mean free path, some of the electrons travel through the channel without experiencing a single scattering event  projectile-like motion (“ballistic transport”) The average velocity of carriers exceeds vsat e.g. 35% for L = 0.12 mm NMOSFET Effectively, vsat and esat increase when L is very small

Summary: NMOSFET I-V Linear region: Saturation region:

PMOSFET I-V with Velocity Saturation Linear region: Saturation region: