Copyright ©2009 by Pearson Higher Education, Inc. Upper Saddle River, New Jersey All rights reserved. Digital Fundamentals, Tenth Edition Thomas L. Floyd Figure 7.1 Two versions of SET-RESET (S-R) latches. Open files F07-01(a) and (b) and verify the operation of both latches.

Copyright ©2009 by Pearson Higher Education, Inc. Upper Saddle River, New Jersey All rights reserved. Digital Fundamentals, Tenth Edition Thomas L. Floyd Figure 7.2 Negative-OR equivalent of the NAND gate S-R latch in Figure 7–1(b). __

Copyright ©2009 by Pearson Higher Education, Inc. Upper Saddle River, New Jersey All rights reserved. Digital Fundamentals, Tenth Edition Thomas L. Floyd Figure 7.3 The three modes of basic S-R latch operation (SET, RESET, no-change) and the invalid condition. __

Copyright ©2009 by Pearson Higher Education, Inc. Upper Saddle River, New Jersey All rights reserved. Digital Fundamentals, Tenth Edition Thomas L. Floyd Figure 7.4 Logic symbols for the S-R and S-R latch. ____

Copyright ©2009 by Pearson Higher Education, Inc. Upper Saddle River, New Jersey All rights reserved. Digital Fundamentals, Tenth Edition Thomas L. Floyd Figure 7.5

Copyright ©2009 by Pearson Higher Education, Inc. Upper Saddle River, New Jersey All rights reserved. Digital Fundamentals, Tenth Edition Thomas L. Floyd Figure 7.6 The S-R latch used to eliminate switch contact bounce. __

Copyright ©2009 by Pearson Higher Education, Inc. Upper Saddle River, New Jersey All rights reserved. Digital Fundamentals, Tenth Edition Thomas L. Floyd Figure 7.7 The 74LS279A quad S-R latch. __

Copyright ©2009 by Pearson Higher Education, Inc. Upper Saddle River, New Jersey All rights reserved. Digital Fundamentals, Tenth Edition Thomas L. Floyd Figure 7.8 A gated S-R latch.

Copyright ©2009 by Pearson Higher Education, Inc. Upper Saddle River, New Jersey All rights reserved. Digital Fundamentals, Tenth Edition Thomas L. Floyd Figure 7.9

Copyright ©2009 by Pearson Higher Education, Inc. Upper Saddle River, New Jersey All rights reserved. Digital Fundamentals, Tenth Edition Thomas L. Floyd Figure 7.10 A gated D latch.

Copyright ©2009 by Pearson Higher Education, Inc. Upper Saddle River, New Jersey All rights reserved. Digital Fundamentals, Tenth Edition Thomas L. Floyd Figure 7.11

Copyright ©2009 by Pearson Higher Education, Inc. Upper Saddle River, New Jersey All rights reserved. Digital Fundamentals, Tenth Edition Thomas L. Floyd Figure 7.12 The 74LS75 quad gated D latches.

Copyright ©2009 by Pearson Higher Education, Inc. Upper Saddle River, New Jersey All rights reserved. Digital Fundamentals, Tenth Edition Thomas L. Floyd Figure 7.13 Edge-triggered flip-flop logic symbols (top: positive edge-triggered; bottom: negative edge-triggered).

Copyright ©2009 by Pearson Higher Education, Inc. Upper Saddle River, New Jersey All rights reserved. Digital Fundamentals, Tenth Edition Thomas L. Floyd Figure 7.14 Operation of a positive edge-triggered S-R flip-flop.

Copyright ©2009 by Pearson Higher Education, Inc. Upper Saddle River, New Jersey All rights reserved. Digital Fundamentals, Tenth Edition Thomas L. Floyd Figure 7.15

Copyright ©2009 by Pearson Higher Education, Inc. Upper Saddle River, New Jersey All rights reserved. Digital Fundamentals, Tenth Edition Thomas L. Floyd Figure 7.16

Copyright ©2009 by Pearson Higher Education, Inc. Upper Saddle River, New Jersey All rights reserved. Digital Fundamentals, Tenth Edition Thomas L. Floyd Figure 7.17 Edge triggering.

Copyright ©2009 by Pearson Higher Education, Inc. Upper Saddle River, New Jersey All rights reserved. Digital Fundamentals, Tenth Edition Thomas L. Floyd Figure 7.18 Flip-flop making a transition from the RESET state to the SET state on the positive-going edge of the clock pulse.

Copyright ©2009 by Pearson Higher Education, Inc. Upper Saddle River, New Jersey All rights reserved. Digital Fundamentals, Tenth Edition Thomas L. Floyd Figure 7.19 Flip-flop making a transition from the SET state to the RESET state on the positive-going edge of the clock pulse.

Copyright ©2009 by Pearson Higher Education, Inc. Upper Saddle River, New Jersey All rights reserved. Digital Fundamentals, Tenth Edition Thomas L. Floyd Figure 7.20 A positive edge-triggered D flip-flop formed with an S-R flip-flop and an inverter.

Copyright ©2009 by Pearson Higher Education, Inc. Upper Saddle River, New Jersey All rights reserved. Digital Fundamentals, Tenth Edition Thomas L. Floyd Figure 7.21

Copyright ©2009 by Pearson Higher Education, Inc. Upper Saddle River, New Jersey All rights reserved. Digital Fundamentals, Tenth Edition Thomas L. Floyd Figure 7.22 A simplified logic diagram for a positive edge-triggered J-K flip-flop.

Copyright ©2009 by Pearson Higher Education, Inc. Upper Saddle River, New Jersey All rights reserved. Digital Fundamentals, Tenth Edition Thomas L. Floyd Figure 7.23 Transitions illustrating the toggle operation when J = 1 and K = 1.

Copyright ©2009 by Pearson Higher Education, Inc. Upper Saddle River, New Jersey All rights reserved. Digital Fundamentals, Tenth Edition Thomas L. Floyd Figure 7.24

Copyright ©2009 by Pearson Higher Education, Inc. Upper Saddle River, New Jersey All rights reserved. Digital Fundamentals, Tenth Edition Thomas L. Floyd Figure 7.25

Copyright ©2009 by Pearson Higher Education, Inc. Upper Saddle River, New Jersey All rights reserved. Digital Fundamentals, Tenth Edition Thomas L. Floyd Figure 7.26 Logic symbol for a J-K flip-flop with active-LOW preset and clear inputs.

Copyright ©2009 by Pearson Higher Education, Inc. Upper Saddle River, New Jersey All rights reserved. Digital Fundamentals, Tenth Edition Thomas L. Floyd Figure 7.27 Logic diagram for a basic J-K flip-flop with active-LOW preset and clear inputs.

Copyright ©2009 by Pearson Higher Education, Inc. Upper Saddle River, New Jersey All rights reserved. Digital Fundamentals, Tenth Edition Thomas L. Floyd Figure 7.28 Open file F07-28 to verify the operation.

Copyright ©2009 by Pearson Higher Education, Inc. Upper Saddle River, New Jersey All rights reserved. Digital Fundamentals, Tenth Edition Thomas L. Floyd Figure 7.29 Logic symbols for the 74AHC74 dual positive edge-triggered D flip-flop.

Copyright ©2009 by Pearson Higher Education, Inc. Upper Saddle River, New Jersey All rights reserved. Digital Fundamentals, Tenth Edition Thomas L. Floyd Figure 7.30 Logic symbols for the 74HC112 dual negative edge-triggered J-K flip-flop.

Copyright ©2009 by Pearson Higher Education, Inc. Upper Saddle River, New Jersey All rights reserved. Digital Fundamentals, Tenth Edition Thomas L. Floyd Figure 7.31

Copyright ©2009 by Pearson Higher Education, Inc. Upper Saddle River, New Jersey All rights reserved. Digital Fundamentals, Tenth Edition Thomas L. Floyd Figure 7.32 Propagation delays, clock to output.

Copyright ©2009 by Pearson Higher Education, Inc. Upper Saddle River, New Jersey All rights reserved. Digital Fundamentals, Tenth Edition Thomas L. Floyd Figure 7.33 Propagation delays, preset input to output and clear input to output.

Copyright ©2009 by Pearson Higher Education, Inc. Upper Saddle River, New Jersey All rights reserved. Digital Fundamentals, Tenth Edition Thomas L. Floyd Figure 7.34 Set-up time (t s ). The logic level must be present on the D input for a time equal to or greater than t s before the triggering edge of the clock pulse for reliable data entry.

Copyright ©2009 by Pearson Higher Education, Inc. Upper Saddle River, New Jersey All rights reserved. Digital Fundamentals, Tenth Edition Thomas L. Floyd Figure 7.35 Hold time (t h ). The logic level must remain on the D input for a time equal to or greater than t h after the triggering edge of the clock pulse for reliable data entry.

Copyright ©2009 by Pearson Higher Education, Inc. Upper Saddle River, New Jersey All rights reserved. Digital Fundamentals, Tenth Edition Thomas L. Floyd Figure 7.36 Example of flip-flops used in a basic register for parallel data storage.

Copyright ©2009 by Pearson Higher Education, Inc. Upper Saddle River, New Jersey All rights reserved. Digital Fundamentals, Tenth Edition Thomas L. Floyd Figure 7.37 The J-K flip-flop as a divide-by-2 device. Q is one-half the frequency of CLK.

Copyright ©2009 by Pearson Higher Education, Inc. Upper Saddle River, New Jersey All rights reserved. Digital Fundamentals, Tenth Edition Thomas L. Floyd Figure 7.38 Example of two J-K flip-flops used to divide the clock frequency by 4. Q A is one-half and Q B is one-fourth the frequency of CLK.

Copyright ©2009 by Pearson Higher Education, Inc. Upper Saddle River, New Jersey All rights reserved. Digital Fundamentals, Tenth Edition Thomas L. Floyd Figure 7.39

Copyright ©2009 by Pearson Higher Education, Inc. Upper Saddle River, New Jersey All rights reserved. Digital Fundamentals, Tenth Edition Thomas L. Floyd Figure 7.40

Copyright ©2009 by Pearson Higher Education, Inc. Upper Saddle River, New Jersey All rights reserved. Digital Fundamentals, Tenth Edition Thomas L. Floyd Figure 7.41 Flip-flops used to generate a binary count sequence. Two repetitions (00, 01, 10, 11) are shown.

Copyright ©2009 by Pearson Higher Education, Inc. Upper Saddle River, New Jersey All rights reserved. Digital Fundamentals, Tenth Edition Thomas L. Floyd Figure 7.42

Copyright ©2009 by Pearson Higher Education, Inc. Upper Saddle River, New Jersey All rights reserved. Digital Fundamentals, Tenth Edition Thomas L. Floyd Figure 7.43

Copyright ©2009 by Pearson Higher Education, Inc. Upper Saddle River, New Jersey All rights reserved. Digital Fundamentals, Tenth Edition Thomas L. Floyd Figure 7.44 A simple one-shot circuit.

Copyright ©2009 by Pearson Higher Education, Inc. Upper Saddle River, New Jersey All rights reserved. Digital Fundamentals, Tenth Edition Thomas L. Floyd Figure 7.45 Basic one-shot logic symbols. CX and RX stand for external components.

Copyright ©2009 by Pearson Higher Education, Inc. Upper Saddle River, New Jersey All rights reserved. Digital Fundamentals, Tenth Edition Thomas L. Floyd Figure 7.46 Nonretriggerable one-shot action.

Copyright ©2009 by Pearson Higher Education, Inc. Upper Saddle River, New Jersey All rights reserved. Digital Fundamentals, Tenth Edition Thomas L. Floyd Figure 7.47 Retriggerable one-shot action.

Copyright ©2009 by Pearson Higher Education, Inc. Upper Saddle River, New Jersey All rights reserved. Digital Fundamentals, Tenth Edition Thomas L. Floyd Figure 7.48 Logic symbols for the nonretriggerable one-shot.

Copyright ©2009 by Pearson Higher Education, Inc. Upper Saddle River, New Jersey All rights reserved. Digital Fundamentals, Tenth Edition Thomas L. Floyd Figure 7.49 Three ways to set the pulse width of a

Copyright ©2009 by Pearson Higher Education, Inc. Upper Saddle River, New Jersey All rights reserved. Digital Fundamentals, Tenth Edition Thomas L. Floyd Figure 7.50 Logic symbol for the 74LS122 retriggerable one-shot.

Copyright ©2009 by Pearson Higher Education, Inc. Upper Saddle River, New Jersey All rights reserved. Digital Fundamentals, Tenth Edition Thomas L. Floyd Figure 7.51

Copyright ©2009 by Pearson Higher Education, Inc. Upper Saddle River, New Jersey All rights reserved. Digital Fundamentals, Tenth Edition Thomas L. Floyd Figure 7.52 A sequential timing circuit using three 74LS122 one-shots.

Copyright ©2009 by Pearson Higher Education, Inc. Upper Saddle River, New Jersey All rights reserved. Digital Fundamentals, Tenth Edition Thomas L. Floyd Figure 7.53 Internal functional diagram of a 555 timer (pin numbers are in parentheses).

Copyright ©2009 by Pearson Higher Education, Inc. Upper Saddle River, New Jersey All rights reserved. Digital Fundamentals, Tenth Edition Thomas L. Floyd Figure 7.54 The 555 timer connected as a one-shot.

Copyright ©2009 by Pearson Higher Education, Inc. Upper Saddle River, New Jersey All rights reserved. Digital Fundamentals, Tenth Edition Thomas L. Floyd Figure 7.55 One-shot operation of the 555 timer.

Copyright ©2009 by Pearson Higher Education, Inc. Upper Saddle River, New Jersey All rights reserved. Digital Fundamentals, Tenth Edition Thomas L. Floyd Figure 7.56 Basic astable multivibrator using a Schmitt trigger.

Copyright ©2009 by Pearson Higher Education, Inc. Upper Saddle River, New Jersey All rights reserved. Digital Fundamentals, Tenth Edition Thomas L. Floyd Figure 7.57 The 555 timer connected as an astable multivibrator (oscillator).

Copyright ©2009 by Pearson Higher Education, Inc. Upper Saddle River, New Jersey All rights reserved. Digital Fundamentals, Tenth Edition Thomas L. Floyd Figure 7.58 Operation of the 555 timer in the astable mode.

Copyright ©2009 by Pearson Higher Education, Inc. Upper Saddle River, New Jersey All rights reserved. Digital Fundamentals, Tenth Edition Thomas L. Floyd Figure 7.59 Frequency of oscillation as a function of C 1 and R 1 + 2R 2. The sloped lines are values of R 1 + 2R 2.

Copyright ©2009 by Pearson Higher Education, Inc. Upper Saddle River, New Jersey All rights reserved. Digital Fundamentals, Tenth Edition Thomas L. Floyd Figure 7.60 The addition of diode D 1 allows the duty cycle of the output to be adjusted to less than 50 percent by making R 1 < R 2.

Copyright ©2009 by Pearson Higher Education, Inc. Upper Saddle River, New Jersey All rights reserved. Digital Fundamentals, Tenth Edition Thomas L. Floyd Figure 7.61 Open file F07-61 to verify operation.

Copyright ©2009 by Pearson Higher Education, Inc. Upper Saddle River, New Jersey All rights reserved. Digital Fundamentals, Tenth Edition Thomas L. Floyd Figure 7.62 Two-phase clock generator with ideal waveforms. Open file F07-62 and verify the operation.

Copyright ©2009 by Pearson Higher Education, Inc. Upper Saddle River, New Jersey All rights reserved. Digital Fundamentals, Tenth Edition Thomas L. Floyd Figure 7.63 Oscilloscope displays for the circuit in Figure 7–62.

Copyright ©2009 by Pearson Higher Education, Inc. Upper Saddle River, New Jersey All rights reserved. Digital Fundamentals, Tenth Edition Thomas L. Floyd Figure 7.64 Two-phase clock generator using negative edge-triggered flip-flop to eliminate glitches. Open file F07-64 and verify the operation.

Copyright ©2009 by Pearson Higher Education, Inc. Upper Saddle River, New Jersey All rights reserved. Digital Fundamentals, Tenth Edition Thomas L. Floyd Figure 7.65 Block diagram of the traffic signal control system.

Copyright ©2009 by Pearson Higher Education, Inc. Upper Saddle River, New Jersey All rights reserved. Digital Fundamentals, Tenth Edition Thomas L. Floyd Figure 7.66 Block diagram of the timing circuits.

Copyright ©2009 by Pearson Higher Education, Inc. Upper Saddle River, New Jersey All rights reserved. Digital Fundamentals, Tenth Edition Thomas L. Floyd Figure 7.67 The timing circuits.

Copyright ©2009 by Pearson Higher Education, Inc. Upper Saddle River, New Jersey All rights reserved. Digital Fundamentals, Tenth Edition Thomas L. Floyd Figure 7.68 Multisim screen for the timing circuits. The switches are for test purposes only.

Copyright ©2009 by Pearson Higher Education, Inc. Upper Saddle River, New Jersey All rights reserved. Digital Fundamentals, Tenth Edition Thomas L. Floyd Figure 7.69 Simulation of the timer circuits.

Copyright ©2009 by Pearson Higher Education, Inc. Upper Saddle River, New Jersey All rights reserved. Digital Fundamentals, Tenth Edition Thomas L. Floyd Figure 7.70

Copyright ©2009 by Pearson Higher Education, Inc. Upper Saddle River, New Jersey All rights reserved. Digital Fundamentals, Tenth Edition Thomas L. Floyd Figure 7.71

Copyright ©2009 by Pearson Higher Education, Inc. Upper Saddle River, New Jersey All rights reserved. Digital Fundamentals, Tenth Edition Thomas L. Floyd Figure 7.72

Copyright ©2009 by Pearson Higher Education, Inc. Upper Saddle River, New Jersey All rights reserved. Digital Fundamentals, Tenth Edition Thomas L. Floyd Figure 7.73

Copyright ©2009 by Pearson Higher Education, Inc. Upper Saddle River, New Jersey All rights reserved. Digital Fundamentals, Tenth Edition Thomas L. Floyd Figure 7.74

Copyright ©2009 by Pearson Higher Education, Inc. Upper Saddle River, New Jersey All rights reserved. Digital Fundamentals, Tenth Edition Thomas L. Floyd Figure 7.75

Copyright ©2009 by Pearson Higher Education, Inc. Upper Saddle River, New Jersey All rights reserved. Digital Fundamentals, Tenth Edition Thomas L. Floyd Figure 7.76

Copyright ©2009 by Pearson Higher Education, Inc. Upper Saddle River, New Jersey All rights reserved. Digital Fundamentals, Tenth Edition Thomas L. Floyd Figure 7.77

Copyright ©2009 by Pearson Higher Education, Inc. Upper Saddle River, New Jersey All rights reserved. Digital Fundamentals, Tenth Edition Thomas L. Floyd Figure 7.78

Copyright ©2009 by Pearson Higher Education, Inc. Upper Saddle River, New Jersey All rights reserved. Digital Fundamentals, Tenth Edition Thomas L. Floyd Figure 7.79

Copyright ©2009 by Pearson Higher Education, Inc. Upper Saddle River, New Jersey All rights reserved. Digital Fundamentals, Tenth Edition Thomas L. Floyd Figure 7.80

Copyright ©2009 by Pearson Higher Education, Inc. Upper Saddle River, New Jersey All rights reserved. Digital Fundamentals, Tenth Edition Thomas L. Floyd Figure 7.81

Copyright ©2009 by Pearson Higher Education, Inc. Upper Saddle River, New Jersey All rights reserved. Digital Fundamentals, Tenth Edition Thomas L. Floyd Figure 7.82

Copyright ©2009 by Pearson Higher Education, Inc. Upper Saddle River, New Jersey All rights reserved. Digital Fundamentals, Tenth Edition Thomas L. Floyd Figure 7.83

Copyright ©2009 by Pearson Higher Education, Inc. Upper Saddle River, New Jersey All rights reserved. Digital Fundamentals, Tenth Edition Thomas L. Floyd Figure 7.84

Copyright ©2009 by Pearson Higher Education, Inc. Upper Saddle River, New Jersey All rights reserved. Digital Fundamentals, Tenth Edition Thomas L. Floyd Figure 7.85

Copyright ©2009 by Pearson Higher Education, Inc. Upper Saddle River, New Jersey All rights reserved. Digital Fundamentals, Tenth Edition Thomas L. Floyd Figure 7.86

Copyright ©2009 by Pearson Higher Education, Inc. Upper Saddle River, New Jersey All rights reserved. Digital Fundamentals, Tenth Edition Thomas L. Floyd Figure 7.87

Copyright ©2009 by Pearson Higher Education, Inc. Upper Saddle River, New Jersey All rights reserved. Digital Fundamentals, Tenth Edition Thomas L. Floyd Figure 7.88

Copyright ©2009 by Pearson Higher Education, Inc. Upper Saddle River, New Jersey All rights reserved. Digital Fundamentals, Tenth Edition Thomas L. Floyd Figure 7.89

Copyright ©2009 by Pearson Higher Education, Inc. Upper Saddle River, New Jersey All rights reserved. Digital Fundamentals, Tenth Edition Thomas L. Floyd Figure 7.90

Copyright ©2009 by Pearson Higher Education, Inc. Upper Saddle River, New Jersey All rights reserved. Digital Fundamentals, Tenth Edition Thomas L. Floyd Figure 7.91

Copyright ©2009 by Pearson Higher Education, Inc. Upper Saddle River, New Jersey All rights reserved. Digital Fundamentals, Tenth Edition Thomas L. Floyd Figure 7.92

Copyright ©2009 by Pearson Higher Education, Inc. Upper Saddle River, New Jersey All rights reserved. Digital Fundamentals, Tenth Edition Thomas L. Floyd Figure 7.93

Copyright ©2009 by Pearson Higher Education, Inc. Upper Saddle River, New Jersey All rights reserved. Digital Fundamentals, Tenth Edition Thomas L. Floyd Figure 7.94

Copyright ©2009 by Pearson Higher Education, Inc. Upper Saddle River, New Jersey All rights reserved. Digital Fundamentals, Tenth Edition Thomas L. Floyd Figure 7.95

Copyright ©2009 by Pearson Higher Education, Inc. Upper Saddle River, New Jersey All rights reserved. Digital Fundamentals, Tenth Edition Thomas L. Floyd Figure 7.96

Copyright ©2009 by Pearson Higher Education, Inc. Upper Saddle River, New Jersey All rights reserved. Digital Fundamentals, Tenth Edition Thomas L. Floyd Figure 7.97

Copyright ©2009 by Pearson Higher Education, Inc. Upper Saddle River, New Jersey All rights reserved. Digital Fundamentals, Tenth Edition Thomas L. Floyd Figure 7.98

Copyright ©2009 by Pearson Higher Education, Inc. Upper Saddle River, New Jersey All rights reserved. Digital Fundamentals, Tenth Edition Thomas L. Floyd Figure 7.99

Copyright ©2009 by Pearson Higher Education, Inc. Upper Saddle River, New Jersey All rights reserved. Digital Fundamentals, Tenth Edition Thomas L. Floyd Figure 7.100

Copyright ©2009 by Pearson Higher Education, Inc. Upper Saddle River, New Jersey All rights reserved. Digital Fundamentals, Tenth Edition Thomas L. Floyd Figure 7.101

Copyright ©2009 by Pearson Higher Education, Inc. Upper Saddle River, New Jersey All rights reserved. Digital Fundamentals, Tenth Edition Thomas L. Floyd Figure 7.102

Copyright ©2009 by Pearson Higher Education, Inc. Upper Saddle River, New Jersey All rights reserved. Digital Fundamentals, Tenth Edition Thomas L. Floyd Figure 7.103

Copyright ©2009 by Pearson Higher Education, Inc. Upper Saddle River, New Jersey All rights reserved. Digital Fundamentals, Tenth Edition Thomas L. Floyd Figure 7.104

Copyright ©2009 by Pearson Higher Education, Inc. Upper Saddle River, New Jersey All rights reserved. Digital Fundamentals, Tenth Edition Thomas L. Floyd Figure 7.105

Copyright ©2009 by Pearson Higher Education, Inc. Upper Saddle River, New Jersey All rights reserved. Digital Fundamentals, Tenth Edition Thomas L. Floyd Figure 7.106

Copyright ©2009 by Pearson Higher Education, Inc. Upper Saddle River, New Jersey All rights reserved. Digital Fundamentals, Tenth Edition Thomas L. Floyd Figure 7.107