1. Introduction to Chapter 5  Logic circuits studied so far have outputs that respond immediately to inputs at some instant in time.  We now introduce the concept of memory. The flip-flop, abbreviated FF, is a key memory element.  The outputs of a flip flop are and  Q is understood to be the normal output, is always the opposite.  When the normal output (Q) is placed in the high or 1 state we say the FF has been set.  When the normal output (Q) is placed in the low or 0 state we say the FF has been cleared or reset. Ronald Tocci/Neal Widmer/Gregory Moss Digital Systems: Principles and Applications, e Copyright ©2007 by Pearson Education, Inc. Columbus, OH 43235 All rights reserved..

2. 5-1 NAND Gate Latch  The NAND gate latch or simply latch is a basic FF.  The inputs are set and clear (reset)  The inputs are active low, that is, the output will change when the input is pulsed low.  When the latch is set  When the latch is clear or reset Ronald Tocci/Neal Widmer/Gregory Moss Digital Systems: Principles and Applications, 10e Copyright ©2007 by Pearson Education, Inc. Columbus, OH 43235 All rights reserved..

3. 5-1 NAND Gate Latch  Summary of the NAND latch: SET = RESET = 1. Normal resting state, outputs remain in state prior to input. SET = 0, RESET = 1. Q will go high and remain high even if the SET input goes high. SET = 1, RESET = 0. Q will go low and remain low even if the RESET input goes high. SET = RESET = 0. Output is unpredictable because the latch is being set and reset at the same time. Ronald Tocci/Neal Widmer/Gregory Moss Digital Systems: Principles and Applications, 10e Copyright ©2007 by Pearson Education, Inc. Columbus, OH 43235 All rights reserved..

4. 5-2 NOR Gate Latch  The NOR latch is similar to the NAND latch except that the outputs are reversed.  The SET and RESET inputs are active high, that is, the output will change when the input is pulsed high.  In order to ensure that a FF begins operation at a known level, a pulse may be applied to the SET or RESET inputs when a device is powered up. Ronald Tocci/Neal Widmer/Gregory Moss Digital Systems: Principles and Applications, 10e Copyright ©2007 by Pearson Education, Inc. Columbus, OH 43235 All rights reserved..

5. 5-3 Troubleshooting Case Study  Analyze and describe the operation of the circuit shown. Ronald Tocci/Neal Widmer/Gregory Moss Digital Systems: Principles and Applications, 10e Copyright ©2007 by Pearson Education, Inc. Columbus, OH 43235 All rights reserved..

6. 5-4 Digital Pulses  Signals that switch between active and inactive states are called pulse waveforms. A positive pulse has an active high level. A negative pulse has an active low level. Ronald Tocci/Neal Widmer/Gregory Moss Digital Systems: Principles and Applications, 10e Copyright ©2007 by Pearson Education, Inc. Columbus, OH 43235 All rights reserved..

7. 5-5 Clock Signals and Clocked Flip-Flops  Asynchronous system – outputs can change state at any time the input(s) change.  Synchronous system – output can change state only at a specific time in the clock cycle. The clock signal is a rectangular pulse train or square wave. Positive going transition (PGT) – when clock pulse goes from 0 to 1. Negative going transition (NGT) – when clock pulse goes from 1 to 0. Transitions are also called edges. Ronald Tocci/Neal Widmer/Gregory Moss Digital Systems: Principles and Applications, 10e Copyright ©2007 by Pearson Education, Inc. Columbus, OH 43235 All rights reserved..

8. 5-5 Clock Signals and Clocked Flip-Flops  Clocked FFs change state on one or the other clock transitions. Some common characteristics: Clock inputs are labeled CLK, CK, or CP. A small triangle at the CLK input indicates that the input is activated with a PGT. A bubble and a triangle indicates that the CLK input is activated with a NGT. Control inputs have an effect on the output only at the active clock transition (NGT or PGT). These are also called synchronous control inputs. The control inputs get the FF outputs ready to change, but the change is not triggered until the CLK edge. Ronald Tocci/Neal Widmer/Gregory Moss Digital Systems: Principles and Applications, 10e Copyright ©2007 by Pearson Education, Inc. Columbus, OH 43235 All rights reserved..

9. 5-5 Clock Signals and Clocked Flip-Flops  Setup time (t S ) is the minimum time interval before the active CLK transition that the control input must be kept at the proper level.  Hold time (t H ) is the time following the active transition of the CLK during which the control input must kept at the proper level. Ronald Tocci/Neal Widmer/Gregory Moss Digital Systems: Principles and Applications, 10e Copyright ©2007 by Pearson Education, Inc. Columbus, OH 43235 All rights reserved..

10. 5-6 Clocked S-R Flip-Flop  The SET-RESET (or SET-CLEAR) FF will change states at the positive going or negative going clock edge. Ronald Tocci/Neal Widmer/Gregory Moss Digital Systems: Principles and Applications, 10e Copyright ©2007 by Pearson Education, Inc. Columbus, OH 43235 All rights reserved..

11. 5-7 Clocked J-K Flip-Flop  Operates like the S-C FF. J is set, K is clear.  When J and K are both high the output is toggled from whatever state it is in to the opposite state.  May be positive going or negative going clock trigger.  Has the ability to do everything the S-C FF does, plus operate in toggle mode. Ronald Tocci/Neal Widmer/Gregory Moss Digital Systems: Principles and Applications, 10e Copyright ©2007 by Pearson Education, Inc. Columbus, OH 43235 All rights reserved..

12. 5-8 Clocked D Flip-Flop  One data input.  The output changes to the value of the input at either the positive going or negative going clock trigger.  May be implemented with a J-K FF by tying the J input to the K input through an inverter.  Useful for parallel data transfer. Ronald Tocci/Neal Widmer/Gregory Moss Digital Systems: Principles and Applications, 10e Copyright ©2007 by Pearson Education, Inc. Columbus, OH 43235 All rights reserved..

13. 5-9 D Latch (Transparent Latch)  One data input.  The clock has been replaced by an enable line.  The device is NOT edge triggered.  The output follows the input only when EN is high. Ronald Tocci/Neal Widmer/Gregory Moss Digital Systems: Principles and Applications, 10e Copyright ©2007 by Pearson Education, Inc. Columbus, OH 43235 All rights reserved..

14. 5-10 Asynchronous Inputs  Inputs that depend on the clock are synchronous.  Most clocked FFs have asynchronous inputs that do not depend on the clock.  The labels PRE and CLR are used for asynchronous inputs.  Active low asynchronous inputs will have a bar over the labels and inversion bubbles.  If the asynchronous inputs are not used they will be tied to their inactive state. Ronald Tocci/Neal Widmer/Gregory Moss Digital Systems: Principles and Applications, 10e Copyright ©2007 by Pearson Education, Inc. Columbus, OH 43235 All rights reserved..

15. 5-11 IEEE/ANSI Symbols  Note the differences in the representations below. Ronald Tocci/Neal Widmer/Gregory Moss Digital Systems: Principles and Applications, 10e Copyright ©2007 by Pearson Education, Inc. Columbus, OH 43235 All rights reserved..

16. 5-12 Flip-Flop Timing Considerations  Important timing parameters: Setup and hold times Propagation delay – the time for a signal at the input to be shown at the output. Maximum clocking frequency – highest clock frequency that will give a reliable output. Clock pulse high and low times – minimum time that clock must high before going low, and low before gong high. Ronald Tocci/Neal Widmer/Gregory Moss Digital Systems: Principles and Applications, 10e Copyright ©2007 by Pearson Education, Inc. Columbus, OH 43235 All rights reserved..

17. 5-12 Flip-Flop Timing Considerations  Important timing parameters (continued) Asynchronous active pulse width – the minimum time PRESET or CLEAR must be held for the FF to set or clear reliably. Clock transition times – maximum time for the clock transitions, generally less than 50 ns for TTL or 200 ns for CMOS devices. Ronald Tocci/Neal Widmer/Gregory Moss Digital Systems: Principles and Applications, 10e Copyright ©2007 by Pearson Education, Inc. Columbus, OH 43235 All rights reserved..

18. 5-13 Potential Timing Problems in FF Circuits  When the output of one FF is connected to the input of another FF and both devices are triggered by the same clock, there is a potential timing problem.  Propagation delay may cause unpredictable outputs.  The low hold time parameter of most FFs mean this won’t normally be a problem. Ronald Tocci/Neal Widmer/Gregory Moss Digital Systems: Principles and Applications, 10e Copyright ©2007 by Pearson Education, Inc. Columbus, OH 43235 All rights reserved..

19. 5-14 Flip-Flop Applications  Examples of applications: Counting Storing binary data Transferring binary data between locations  Many FF applications are categorized as sequential, which means that the output follows a predetermined sequence of states. Ronald Tocci/Neal Widmer/Gregory Moss Digital Systems: Principles and Applications, 10e Copyright ©2007 by Pearson Education, Inc. Columbus, OH 43235 All rights reserved..

20. 5-15 Flip-Flop Synchronization  Most systems are primarily synchronous in operation, in that changes depend on the clock.  Asynchronous and synchronous operations are often combined.  The random nature of asynchronous inputs can result in unpredictable results.  Example 5-11 describes the problem and a solution. Ronald Tocci/Neal Widmer/Gregory Moss Digital Systems: Principles and Applications, 10e Copyright ©2007 by Pearson Education, Inc. Columbus, OH 43235 All rights reserved..

21. 5-16 Detecting an Input Sequence  FFs provide features that pure combinational logic gates do not.  If an output is desired only when inputs change state in sequence, an arrangement similar to figure 5-41 can be used. Ronald Tocci/Neal Widmer/Gregory Moss Digital Systems: Principles and Applications, 10e Copyright ©2007 by Pearson Education, Inc. Columbus, OH 43235 All rights reserved..

22. 5-17 Data Storage and Transfer  FFs are commonly used for storage and transfer of data in binary form.  Groups of FFs used for storage are registers.  Data transfers take place when data is moved between registers or FFs.  Synchronous transfers take place at PGT or NGT of clock. Ronald Tocci/Neal Widmer/Gregory Moss Digital Systems: Principles and Applications, 10e Copyright ©2007 by Pearson Education, Inc. Columbus, OH 43235 All rights reserved..

23. 5-17 Data Storage and Transfer  Asynchronous transfers are controlled by PRE and CLR inputs.  Transferring the bits of a register simultaneously is a parallel transfer.  Transferring the bits of a register a bit at a time is a serial transfer. Ronald Tocci/Neal Widmer/Gregory Moss Digital Systems: Principles and Applications, 10e Copyright ©2007 by Pearson Education, Inc. Columbus, OH 43235 All rights reserved..

24. 5-18 Serial Data Transfer: Shift Registers  When FFs are arranged as a shift register, bits will shift with each clock pulse.  FFs used as shift registers must have very low hold time parameters to perform predictably. Modern FFs have t H values well within what is required.  The direction of data shifts will depend on the circuit requirements and the design. Ronald Tocci/Neal Widmer/Gregory Moss Digital Systems: Principles and Applications, 10e Copyright ©2007 by Pearson Education, Inc. Columbus, OH 43235 All rights reserved..

25. 5-18 Serial Data Transfer: Shift Registers  Parallel transfers – register contents are transferred simultaneously with a single clock cycle.  Serial transfers – register contents are transferred one bit at a time, with a clock pulse for each bit.  Serial transfers are slower, but the circuitry is simpler. Parallel transfers are faster, but circuitry is more complex.  Serial and parallel are often combined to exploit the benefits of each. Ronald Tocci/Neal Widmer/Gregory Moss Digital Systems: Principles and Applications, 10e Copyright ©2007 by Pearson Education, Inc. Columbus, OH 43235 All rights reserved..

26. 5-19 Frequency Division and Counting  FFs are often used to divide a frequency as illustrated in Figure 5-47. Here the output frequency is 1/8 th the input (clock) frequency.  The same circuit is also acting as a binary counter. The outputs will count from 000 2 to 111 2 or 0 10 to 7 10  The number of states possible in a counter is the modulus or MOD number. Figure 5-47 is a MOD-8 (2 3 ) counter. If another FF is added it would become a MOD-16 (2 4 ) counter. Ronald Tocci/Neal Widmer/Gregory Moss Digital Systems: Principles and Applications, 10e Copyright ©2007 by Pearson Education, Inc. Columbus, OH 43235 All rights reserved..

27. 5-20 Microcomputer Application  Microprocessor units (MPUs) which will be studied later, perform many functions that involve the use of registers for data transfer and storage.  MPUs may send data to external registers for many purposes, including: Solenoid or relay control Motor starting Device positioning Motor speed controls Ronald Tocci/Neal Widmer/Gregory Moss Digital Systems: Principles and Applications, 10e Copyright ©2007 by Pearson Education, Inc. Columbus, OH 43235 All rights reserved..

28. 5-21 Schmitt-Trigger Devices  Not a FF but shows a memory characteristic  Accepts slow changing signals and produces a signal that transitions quickly.  A Schmitt trigger device will not respond to an input until it exceeds the positive or negative going threshold.  There is a separation between the two threshold levels. This means that the device will “remember” the last threshold exceeded until the input goes to the opposite threshold. Ronald Tocci/Neal Widmer/Gregory Moss Digital Systems: Principles and Applications, 10e Copyright ©2007 by Pearson Education, Inc. Columbus, OH 43235 All rights reserved..

29. 5-22 One-shot (Monostable Multivibrator)  Changes from stable state to quasi-stable state for a period of time determined by external components (usually resistors and capacitors).  Nonretriggerable devices will trigger and return to stable state.  Retriggerable devices can be triggered while in the quasi-stable state to begin another pulse.  One shots are called monostable multivibrators because they have only one stable state.  They are prone to triggering by noise so, tend to be used in simple timing applications. Ronald Tocci/Neal Widmer/Gregory Moss Digital Systems: Principles and Applications, 10e Copyright ©2007 by Pearson Education, Inc. Columbus, OH 43235 All rights reserved..

30. 5-23 Clock Generator Circuits  FFs have two stable states, so are considered bistable multivibrators.  One shots have one stable state and are considered monostable multivibrators.  Astable or free-running multivibrators switch back and forth between two unstable states. This makes it useful for generating clock signals for synchronous circuits. Ronald Tocci/Neal Widmer/Gregory Moss Digital Systems: Principles and Applications, 10e Copyright ©2007 by Pearson Education, Inc. Columbus, OH 43235 All rights reserved..

31. 5-23 Clock Generator Circuits  The astable multivibrators (oscillators) shown in Figures 5-55 and 5-56 are provided for lab or project use and will not be analyzed.  Crystal control may be used if a very stable clock is needed. Crystal control is used in microprocessor based systems and microcomputers where accurate timing intervals are essential. Ronald Tocci/Neal Widmer/Gregory Moss Digital Systems: Principles and Applications, 10e Copyright ©2007 by Pearson Education, Inc. Columbus, OH 43235 All rights reserved..

32. 5-24 Troubleshooting Flip-Flop Circuits  FFs are subject to the same faults that occur in combinational logic circuits discussed in Chapter 4.  Timing problems create some faults and symptoms that are not seen in combinational logic circuits. Ronald Tocci/Neal Widmer/Gregory Moss Digital Systems: Principles and Applications, 10e Copyright ©2007 by Pearson Education, Inc. Columbus, OH 43235 All rights reserved..

33. 5-24 Troubleshooting Flip-Flop Circuits  Open inputs that can trigger a change in state may pick up noise resulting in erratic output.  Example 5-20 describes the process of isolating a shorted output.  Clock skew occurs when CLK signals arrive at different FFs at different times. The fault may be seen only intermittently, or may disappear during testing. Ronald Tocci/Neal Widmer/Gregory Moss Digital Systems: Principles and Applications, 10e Copyright ©2007 by Pearson Education, Inc. Columbus, OH 43235 All rights reserved..

34. 5-25 Sequential Circuits Using HDL  A NAND latch in AHDL AHDL does not require a special designation for output with feedback. Ronald Tocci/Neal Widmer/Gregory Moss Digital Systems: Principles and Applications, 10e Copyright ©2007 by Pearson Education, Inc. Columbus, OH 43235 All rights reserved..

35. 5-25 Sequential Circuits Using HDL  A NAND latch in VHDL VHDL does require a special designation for an output with feedback. Ronald Tocci/Neal Widmer/Gregory Moss Digital Systems: Principles and Applications, 10e Copyright ©2007 by Pearson Education, Inc. Columbus, OH 43235 All rights reserved..

36. 5-26 Edge Triggered Devices  A standard JK FF with 5 inputs and 2 outputs is a fundamental part of sequential logic circuits called a logic primitive.  AHDL uses logic primitives defined in library files to describe FF operation.  VHDL is similar, but allows the designer to explicitly describe logic circuit operation in the code. Ronald Tocci/Neal Widmer/Gregory Moss Digital Systems: Principles and Applications, 10e Copyright ©2007 by Pearson Education, Inc. Columbus, OH 43235 All rights reserved..

37. 5-27 HDL Circuits with Multiple Components  It is possible to graphically describe a circuit that can be converted to HDL, compiled, and loaded into a device. Figure 5-70 is a graphic description of the circuit we studied in Figure 5-47.  Figures 5-71 and 5-72 describe the same counter in AHDL and VHDL respectively.  The complexity of the code is the price the developer pays for being able to precisely tailor components to fit a project. Ronald Tocci/Neal Widmer/Gregory Moss Digital Systems: Principles and Applications, 10e Copyright ©2007 by Pearson Education, Inc. Columbus, OH 43235 All rights reserved...