CALICE/EUDET FEE status C. de LA TAILLE

16 jun 2009 TB meeting FNAL ASICs for CALICE/EUDET 2 First generation ASICs Readout of physics prototypes (ECAL, AHCAL, DHCAL) –Front-end ASICs outside the detector, no power constraint –Multiplexed analog output : digitization and readout in DAQ –FLC_PHY3 for SiW ECAL, (BiCMOS 0.8µm [LAL-Orsay] ) –FLC_SiPM for AHCAL (BiCMOS 0.8µm [LAL-Orsay] ) –DCAL for DHCAL (CMOS 0.25 µm [FNAL] ) Chips used in testbeam –Since 2003 for ECAL, scECAL and AHCAL (20,000 channels) –Foreseen in 2009 for RPC DHCAL (400,000 channels!) –Good overall performance

16 jun 2009 TB meeting FNAL ASICs for CALICE/EUDET 3 Second generation ASICs : ROC chips Add auto-trigger, analog storage, digitization and token-ring readout !!! Include power pulsing : <1 % duty cycle Address integration issues asap Optimize commonalities within CALICE (readout, DAQ…) Build scalable technological prototype (EUDET program) –Testbeam operation of technological proto ? SkiROC HardROC (2006) SPIROC FLC_PHY3 (2003)

16 jun 2009 TB meeting FNAL ASICs for CALICE/EUDET 4 HaRDROC status 240 chips HARDROC1 produced in june 2007 to equip 4-chip and 24-chip RPC and Micromegas detectors –Package PQFP240 –Not completely power-pulsed 400 chips HARDROC2 produced in june 2008 to equip 24-chip RPC and Micromegas for square meter –3 thresholds ( pC) –Power pulsed to <10 µW/ch –Package TQFP160 Essential for readout + DAQ2 validation Full production run : end 2009 –After validation on detector TQFP: t=1.4 mm

16 jun 2009 TB meeting FNAL ASICs for CALICE/EUDET 5 Trigger efficiency measurements FSB0, 100K, 100fF, G=144 NO decoupling cap. 30 fC 10 fC Pedestal Dac unit Channel number 1pC 100 fC piedestal Low gain : DAC Unit ≈ 3 fC High gain : DAC Unit ≈ 1 fC

16 jun 2009 TB meeting FNAL ASICs for CALICE/EUDET 6 Total power on : 100 mW Total power off : 10 µW Power dissipation –1.5 mW/ch continuous –25 µs awake time –7.5 µW/ch with 0.5% duty cycle 10 µW/ch = 24h operation of full slab with 2 AAA batteries ! PA 5.46mA DAC 0.84mA 3 FSB 12.3mA BG 1.2mA SS 9.3mA vddd 0.67mA 3 Discris 7.3mA vddd2 0.4mA (=0 if 40MHz OFF) TOTAL 38mA Trigger 25 µs PWR ON Power pulsing

16 jun 2009 TB meeting FNAL ASICs for CALICE/EUDET 7 Assembled(IPNL) On a GRPC Daisy chain measurement Readout validation with HARDROC

16 jun 2009 TB meeting FNAL ASICs for CALICE/EUDET 8 Slab #1 Slab #2 Slab #3 DIF #1 DIF #2 DIF #3 GRPC Fully equipped large scalable detector to be soon tested in cosmic rays bench and in test beam at CERN in summer 09 [I. Laktineh et al.] Towards technological prototype

16 jun 2009 TB meeting FNAL ASICs for CALICE/EUDET 9 SPIROC for AHCAL Internal input 8-bit DAC (0-5V) for individual SiPM gain adjustment Energy measurement : 14 bits –2 gains (1-10) + 12 bit ADC 1 pe  2000 pe –Variable shaping time from 50ns to 100ns –pe/noise ratio : 11 Auto-trigger on 1/3 pe (50fC) –pe/noise ratio on trigger channel : 24 –Fast shaper : ~10ns –Auto-Trigger on ½ pe Time measurement : –12-bit Bunch Crossing ID –12 bit TDC step~100 ps Analog memory for time and charge measurement : depth = 16 Low consumption : ~25µW per channel (in power pulsing mode) Individually addressable calibration injection capacitance Embedded bandgap for voltage references Embedded 10 bit DAC for trigger threshold and gain selection Multiplexed analog output for physics prototype DAQ 4k internal memory and Daisy chain readout

16 jun 2009 TB meeting FNAL ASICs for CALICE/EUDET 10 SPIROC status 200 chips SPIROC1 produced in nov 2006 –Package PQFP240 –Good analog performance –Bug in ADC ramp : no digital data out 50 chips SPIROC2 produced in june 2008 to equip AHCAL and ECAL EUDET modules –Package TQFP208 –Difficult slow control loading Measurements slowly coming in –Need to produce a list of desired measurements Full production run : end 2009 –After validation on detector

Mathias Reinecke | EUDET Electronics | | Page 11 HBU0 status SPIROC1 Connectors: Signal Power SPIROC2 DIF FPGA CALIB USB / DAQ Flexleads 2 setups available ©M. Reinecke (DESY)

16 jun 2009 TB meeting FNAL ASICs for CALICE/EUDET 12 Performance pedestal Qinj=50fC High gain channel linearity Linearity better than 1% ©W.Shen (Heidelberg) ©Beni (DESY)

16 jun 2009 TB meeting FNAL ASICs for CALICE/EUDET 13 PARISROC 12bit Wilkinson ADC Measurement from PARISROC (sister chip for Water Cerenkov) Wilkinson ADC well suited to multichannel conversion Very good uniformity and linearity Linearity of 12bit Wilkinson ADC Uniformity of 10bit Wilkinson ADC 16 channels superimposed ! First measurements coming in, don’t look as good so far, more work needed…

16 jun 2009 TB meeting FNAL ASICs for CALICE/EUDET 14 SKIROC for W-Si ECAL Silicon Kalorimeter Integrated Read Out Chip (Nov 06) –36 channels with 15 bits Preamp + bi-gain shaper + autotrigger + analog memory + Wilkinson ADC –Digital part outside in a FPGA for lack of time and increased flexibility, but cannot be used on an ASU or FEV –Collaboration with LPC Clermont Noise in low gain shaper rms = 0.9UADC (330µV) MIP = 3 UADC

16 jun 2009 TB meeting FNAL ASICs for CALICE/EUDET 15 SKIROC status SKIROC1 useless with detector (no readout) SPIROC2 used as SKIROC emulator –36 channels only –Limited dynamic range (~500 MIPs) –Tests starting with FEV7 –Noise tests on testboard proceeding (ENC ~ 1 ke-) SKIROC2 to be submitted with production run –Expensive ASIC (70 mm2 = 70 k€) => MPW not worth it –64 channels –95% identical to SPIROC (only preamp differs)

16 jun 2009 TB meeting FNAL ASICs for CALICE/EUDET 16 Other chips developments DIRAC [R. Gaglione IPNL/LAPP] –DHCAL chip with 3 thresholds, larger sensitivity (few fC for GEM & Micromegas), smaller area –Synchronous operation –Good performance so far, tests going on for min threshold. –Second version produced, tests with detector going on ADC developments [J. Lecoq et al. Clermont, D. Dzahini et al. Grenoble] –Pipeline or cyclic 12bit ADC, alternative to Wilkinson –Lower power dissipation, possibly better performance –Now mature prototypes in hand, will be included in a full chip in 2009

16 jun 2009 TB meeting FNAL ASICs for CALICE/EUDET 17 Next steps ASICs –One engineering run with HARDROC3, SPIROC3 and SKIROC2 spring/summer 2009 –Same digital part and interface to DAQ2 –Need testbench results of ROC2 and tests with detector –Several thousands chips will be produced, it will allow first large scale prototypes of EUDET ECAL and AHCAL modules mid 2009 Front-End boards (interface with detector) –Difficulties encountered for ECAL FEV5 with Hardroc –ECAL FEV7 with SPIROC2 packaged and chip-on-board –AHCAL HBU0 in test Readout (interface with DAQ) –First DIFs coming now. Tests starting with IPNL boards

16 jun 2009 TB meeting FNAL ASICs for CALICE/EUDET 18 Third generation ASICs Need to handle all channels independantly –Large modification of digital part –Analog part basically untouched –DAQ part unchanged Choose best ADC Add electronic calibration pulser Need test results from technological prototype –Still some parallel work can start in 2009 Strengthen collaborations

16 jun 2009 TB meeting FNAL ASICs for CALICE/EUDET 19 Engineering run Reticle size : 20x20 mm2 –65 reticles/Wafer Arrangement to be finalized –10 HR3 –3 SP3 –1 SK2 Will be launched as soon as measurements are complete ! –Exp. Beg SKIROC2 SPIROC3 HR3

16 jun 2009 TB meeting FNAL ASICs for CALICE/EUDET 20 Data rate (Spiroc/Skiroc) : naive estimate –Volume : 36ch*16sca*50bits=30 kbit/chip –Conversion time : 16*80 µs = 1.5 ms –Readout speed 5 MHz (could be increased to MHz) –8 chips/DIF line (one FEV only) –Total : 1.5ms *200ns*8 = 50 ms/16 events = 3 ms/evt => 300 Hz during spill Overall readout rate –« Add » 1-10% power pulsing : 3-30 Hz effective rate –Pessimistic as assuming all chips full Note : readout electronics designed for ILC low- occupancy, low rate detector ≠Testbeam !! Test beam with technological prototype

16 jun 2009 TB meeting FNAL ASICs for CALICE/EUDET 21 Summary 2 nd prototypes of HARDROC (DHCAL) and SPIROC (AHCAL+ECAL) submitted in june 08 DAQ part being validated with HaRDROC Power pulsing tests essential now at system level Front-end boards first prototypes coming in –Difficulties with ECAL boards DAQ interface (DIF boards) prototyped One engineering run with all 3 chips (ECAL, DHCAL and AHCAL) beg 2010 : can be used as « production run » Tests are very complex and lagging behind Still need to validate noise, autotrigger, ADC, power pulsing with detector.

16 jun 2009 TB meeting FNAL ASICs for CALICE/EUDET 22 Backup slides

16 jun 2009 TB meeting FNAL ASICs for CALICE/EUDET 23 Read out: token ring Acquisition A/D conv.DAQIDLE MODE Chip 0 Chip 1 Acquisition A/D conv.DAQIDLE MODEIDLE Chip 2 Acquisition A/D conv.IDLE MODEIDLE Chip 3 Acquisition A/D conv.IDLE MODEIDLE Chip 4 Acquisition A/D conv.IDLE MODEIDLEDAQ 1ms (.5%).5ms (.25%) 1% duty cycle99% duty cycle 199ms (99%) Readout architecture common to all calorimeters Minimize data lines & power 5 events3 events 0 event 1 event 0 event Chip 0Chip 1Chip 2Chip 3Chip 4 Data bus ILC beam

16 jun 2009 TB meeting FNAL ASICs for CALICE/EUDET 24 SPIROC : One channel schematic

16 jun 2009 TB meeting FNAL ASICs for CALICE/EUDET 25 FEV5 : new PCB for ECAL Physical prototype Global dimensions : 180*180 mm, thickness 1.2mm pixel dimensions : 4*4 mm 0.15mm <depth<0.17mm 0.6mm< depth<0.7mm