George W. Woodruff School of Mechanical Engineering, Georgia Tech ME4447/6405 ME 4447/6405 Microprocessor Control of Manufacturing Systems and Introduction to Mechatronics Instructor: Professor Charles Ume Lecture #7

George W. Woodruff School of Mechanical Engineering, Georgia Tech ME4447/6405

ME4447/6405 RAM – Random Access Memory “Volatile” – loses contents after power off ROM – Read Only Memory “non-Volatile” Contents must be programmed at the factory EPROM – Electrically Programmable Read Only Memory “non-Volatile” Electrically programmable May be erasable with ultraviolet light if manufacturer included window in chip package Still considered Read Only Memory during normal program execution EEPROM – Electrically Erasable Programmable Read Only Memory “non-Volatile” Electrically programmable and erasable (Note:Sometimes higher voltage than microcontroller voltage may be required) Slower to write to than RAM so still considered Read Only Memory during normal program execution

George W. Woodruff School of Mechanical Engineering, Georgia Tech ME4447/6405 Product Designations found in literature is shown below: Read: MC9S12C32 Device User Guide V01.14 HCS12 Microcontrollers: MC9S12C128 Rev 01.23

George W. Woodruff School of Mechanical Engineering, Georgia Tech ME4447/6405 Product Family Members as of 3/2008

George W. Woodruff School of Mechanical Engineering, Georgia Tech ME4447/6405

ME4447/6405 MC9S12C-Family package options: 48-pin Low-profile Quad Flat Package (LQFP) 52-pin Low-profile Quad Flat Package 80-pin quad flat package (QFP) (Shown)

George W. Woodruff School of Mechanical Engineering, Georgia Tech ME4447/6405 MC9S12C-Family Block Diagram shows available subsystems Figure1-1. MC9S12C-Family Block Diagram

George W. Woodruff School of Mechanical Engineering, Georgia Tech ME4447/6405 Data Direction and Data Register  Data Direction Register (DDR)  Used to indicate direction of data flow in a port  Example configure pins 0, 3, 5 and 7 of port A as output pins  Note: By default all port pins are input pins  DDRA ($0002)should be loaded with: #% or #$A9  Assembly code to accomplish the above: LDAA #$A9 STAA $0002  Data Register  Used to control state of devices connected to output pins  Used to determine state of devices connected to input pins  Suppose 4 different light bulbs are to be turned on and off from these output pins:

George W. Woodruff School of Mechanical Engineering, Georgia Tech ME4447/6405 Data Direction and Data Register  Port A data Register address is $0000 To turn light bulbs connected to PA0 and PA3 on: o Store #% or #$09 at address $0000 –LDAA #$09 –STAA $0000 To turn all light bulbs connected to PA0, PA3, PA5 and PA7 on: Store #% or #$A9 at address $0000 LDAA #$A9 STAA $0000

George W. Woodruff School of Mechanical Engineering, Georgia Tech ME4447/6405 Data Direction and Data Register  Suppose you want to determine state of machines connected to input pins PA1, PA2, PA4 and PA6: You load accumulator A with content of address $0000 In accumulator A: If logic 1 is written in bits 1 and 4 respectively: –That will mean that devices connected to PA1 and PA4 have been turned on In accumulator A: If logic 1 is written in bits 1, 2, 4 and 6: –That will mean that all devices connected to PA1, PA2, PA4 and PA6 are on

George W. Woodruff School of Mechanical Engineering, Georgia Tech ME4447/6405

ME4447/6405

ME4447/6405 Figure 6. Register and Control Bit Assignments (Programming Reference) Excerpt of Detailed Register Map (Device User Guide)

George W. Woodruff School of Mechanical Engineering, Georgia Tech ME4447/

ME4447/6405 Excerpt of Detailed Register Map (Device User Guide)

George W. Woodruff School of Mechanical Engineering, Georgia Tech ME4447/6405

ME4447/6405 Hardware Mode Selection Summary (Reference Manual) MODA, MODB, & MODC may be writable in software after startup, see Reference

George W. Woodruff School of Mechanical Engineering, Georgia Tech ME4447/6405 HCS12 Features 80 pin HCS12 Crystal Frequency is 16 Mhz Clock Frequency is 8 Mhz Therefore, 1 clock cycle = 0.125micro seconds Normal Expanded Wide

George W. Woodruff School of Mechanical Engineering, Georgia Tech ME4447/6405 In Single Chip mode, Ports A, B and E available as general purpose input/output pins In Narrow Expanded Mode, Ports A and B form 16-bit Address and 8-bit Data bus, Port E provides control signals for external devices In Wide Expanded mode, Ports A and B form 16-bit Address and 16- bit Data bus, Port E provides control signals for external devices Hardware Mode External Connections

George W. Woodruff School of Mechanical Engineering, Georgia Tech ME4447/6405 Note: Map depends on state of ROMON and ROMHM bits

George W. Woodruff School of Mechanical Engineering, Georgia Tech ME4447/6405

ME4447/6405 Axiom CML-12C32 Evaluation Board MC9S12C32 Solderless Breadboard Serial Port External SRAM Address Demultiplexer Power Jack MCU Port Reset Oscillator

George W. Woodruff School of Mechanical Engineering, Georgia Tech ME4447/6405 Default Configuration: MODC = 1 MODA = MODB = 0  Single Chip Mode MODA and MODB may be changed in software to permit use of Expanded Wide mode once after each reset Internal Flash Memory is available only if ROMON is enabled At the rising edge of Reset, the state of pin PP[6]/KWP[6]/ROMCTL is latched to the ROMON bit. ROMCTL = 1  ROMON Enabled, Flash memory available ROMCTL = 0  ROMON Disable, Flash memory unavailable For operation in this class, ROMON will be Enabled, so do not pull PP[6] low on Reset!

George W. Woodruff School of Mechanical Engineering, Georgia Tech ME4447/6405 Axiom CML-C32 Single chip mode ROMON Enabled MON12 not in use (CodeWarrior) MODA = 0 MODB = 0 Internal User RAM available: $0800-$0FFF User can put a program in Internal Flash$8000-$FEFF Ports A and B available for use

George W. Woodruff School of Mechanical Engineering, Georgia Tech ME4447/6405 Axiom CML-C32 Single chip mode ROMON Enabled MON12 in use MODA = 0; MODB = 0 Internal User RAM available: $0800-$0DFF  Stack Location: $0E00 – $0E5F  Mon12 RAM Interrupt Vector: $0F8A – 0FFF User can put a program in Internal Flash $8000-$BEFF and Internal RAM Ports A and B available for use MON12 is located here

George W. Woodruff School of Mechanical Engineering, Georgia Tech ME4447/6405 Axiom CML-C32 Expanded Wide mode ROMON Enabled MON12 not in use (CodeWarrior) MODA = 1 MODB = 1 Internal User RAM available: $0800-$0FFF External User RAM available: $0400-$07FF $1000-$7FFF User can put a program in Internal Flash $8000-$FEFF Ports A and B NOT available for use

George W. Woodruff School of Mechanical Engineering, Georgia Tech ME4447/6405 Axiom CML-C32 Expanded Wide mode ROMON Enabled MON12 in use MODA = 1; MODB = 1 Internal User RAM available: $0800-$0DFF (Run AXIDE) Monitor Utility Jump Table: $FF10-$FF67 External User RAM available: $0400-$07FF $1000-$7FFF User can put a program in Internal Flash $8000-$B7FF and RAM Ports A and B NOT available for use MON12 is located here  Stack Location: $0E00 – $0E5F Mon12 RAM Interrupt Vector: $0F8A – 0FFF

George W. Woodruff School of Mechanical Engineering, Georgia Tech ME4447/6405 Interrupt Vector Table Mon12 NOT in use Standard S12C32 Interrupt Jump Table Each vector is 2 bytes. User stores address of interrupt service routine in appropriate vector 0x is same as $: It is used when writing program in C

George W. Woodruff School of Mechanical Engineering, Georgia Tech ME4447/6405 Interrupt Vector Table Mon12 NOT in use Standard S12C32 Interrupt Jump Table Each vector is 2 bytes. User stores address of interrupt service routine in appropriate vector

George W. Woodruff School of Mechanical Engineering, Georgia Tech ME4447/6405 Standard S12C32 Interrupt Jump Table ( MON12 not in use) The user can put the starting address of his/her subroutine Directly in the vector field of the interrupt he/she wants to Use. Example: If the user wants to use the IRQ interrupt, he/she can put the starting address of his/her subroutine directly in vector fields $FFF2 and $FFF3

George W. Woodruff School of Mechanical Engineering, Georgia Tech ME4447/6405 Interrupt Vector Table MON12 in use Standard S12C32 Interrupt Vector Jump Table is not available with MON12 MON12 supplies alternate Interrupt Jump Table User’s interrupt service routine must be stored in $4000-$7FFF (External RAM) if Autostart is to be used Monitor Interrupt Vector Table (CML- C32 User’s Guide)

George W. Woodruff School of Mechanical Engineering, Georgia Tech ME4447/6405 Interrupt Vector Table MON12 in use Standard S12C32 Interrupt Vector Jump Table is not available with MON12 MON12 supplies alternate Interrupt Jump Table User’s interrupt service routine must be stored in $4000-$7FFF if Autostart is to be used Monitor Interrupt Vector Table (CML- C32 User’s Guide) To use the vector table, the user again writes the address of the interrupt service routine to the location given in the table. For example, to use the IRQ interrupt to call an interrupt service routine located at address ISR_ADDR, the user writes the following code: MOVW #$0800, $0FF2 OR MOVW #ISR_ADDR,$0FF2 LDD #$0800 STD $0FF2 During initialization MON12 writes $0000 to all vectors in the Monitor Interrupt vector Table to cause any unscheduled interrupt to cause a trap. Any nonzero value will cause the S12C32 to jump to the interrupt service routine located at that value.

George W. Woodruff School of Mechanical Engineering, Georgia Tech ME4447/6405 Relationship Between Standard S12C32 Interrupt Vectors and MON12 Interrupt Table Vectors When MON12 is in use, it configures the standard interrupt vector table and the user may not override these values. MON12 allocates memory for the Monitor Interrupt Table, located from $0F8A - $0FFF. During initialization, MON12 clears the contents of the Monitor Interrupt Table. If an interrupt occurs and the corresponding vector contains $0000, MON12 perceives this as an error and restarts the monitor program, ending execution of user code. MON12 uses some interrupts to accomplish its tasks, hence uses those vector addresses. In addition, the standard interrupt table is located in Flash EEPROM and cannot be written to using MON12. When writing programs in C, a BDM cable is used to program the HCS12 and the standard interrupt table is used.

George W. Woodruff School of Mechanical Engineering, Georgia Tech ME4447/6405 COMMANDDescription BF Block Fill Memory with Data BR [ ]….Display/Set Breakpoint CALL [ ]Execute Subroutine G [ ]Begin/continue execution of user program HELPDisplay Monitor Commands LOAD [P]Load S-Records into memory, P = Paged S2 MD [ ]Memory Display Bytes MM [ ]Memory Modify Bytes (8 bit values) MW [ ]Memory Modify Words (16 bit values) MOVE [ ]Move a block of memory RDDisplay all CPU registers OFFSET – [arg]Offset for download ProceedProceed / Continue from Breakpoint RM [p,y,x,a,b,c,s]Modify CPU Register Contents STOPAT Trace until address T [ ]Trace Instructions Mon12 Commands

George W. Woodruff School of Mechanical Engineering, Georgia Tech ME4447/6405 Several subroutines from Mon12 exist that are available for performing I/O tasks. Utility subroutines available to the user are as follows:

George W. Woodruff School of Mechanical Engineering, Georgia Tech ME4447/6405 Interrupt Acknowledgement Assume an interrupt is enabled in the main program, e.g. IRQ Signal is received by the MC from IRQ pin –MC will finishing executing the current instructions –I-bit in the CCR is set to 1 (this will cause any incoming maskable interrupt to queue up) –CPU registers are pushed in the Stack –Starting address of the interrupt Sub-routine to be executed is fetched from the IRQ vectors –This Sub-routine is executed and the last instruction is RTI –The execution of the RTI will cause all the data in the Stack to be pulled out and put back in their respective registers –The last 2-byte data pulled out are the Program Counter High and Low bytes address –The MC will use these 2-byte address to know where to get the next instruction to be executed