1. ECE 371 Microprocessor Interfacing
Unit 2 - Introduction to the MC9S12DP256B Microcontroller

2. 16-bit Microcontroller Family (Partial List)
• MC9S12D64
MC9S12DG128B
MC9S12DP256B (our chip)
MC9S12DP512

3. Product Numbering System
MC 9 S12 DP 256 B
Status
Memory type
- 9:flash
Core type
Family
Approximate memory size
Flash revision

4. HCS12 Variants

6. 68HC12 References http://www.freescale.com Lab Computers – Files
products -> microcontrollers -> 16 bit microcontrollers
documentation -> microcontrollers -> 16 bit microcontrollers
Lab Computers – Files

7. INTERNAL FEATURES OF MCS912DP256B
(PARTIAL LIST)
MEMORY
A/D CONVERTER
I/O PORTS
PULSE-WIDTH MODULATON OUTPUTS
SERIAL I/O
WATCH DOG TIMER
TIMER
CONTROLLER AREA NETWORK (CAN) SIGNALS
PULSE ACCUMULATOR

8. INTERNAL MEMORY OF MCS912DP256B
• 12 K BYTES OF RAM
(PROGRAM CODE, VARIABLES, AND STACK)
• 4K BYTES OF EEPROM
(SYSTEM DATA)
• 256K BYTES OF FLASH EEPROM (PROGRAM CODE)
• ALSO 2K BYTES FOR REGISTERS

9. Registers
Programmable
Memory
Manager
Internal
SRAM
CPU
Internal
EEPROM
16-bit Address
64K
Internal
Flash
External
SRAM
256K

12. CONNECTIONS TO THE OUTSIDE WORLD
112 PINS ON MC9S12DP256B CHIP
PORTS
A - 8 BITS
B - 8 BITS
E - 8 BITS
H - 8 BITS
J - 4 BITS
K - 7 BITS
M - 8 BITS
P - 8 BITS
S - 8 BITS
T - 8 BITS
AD0 - 8 BITS
AD1 - 8 BITS
TOTAL: 91 I/O BITS
13 PINS FOR INPUT VOLTAGES
AND GROUND
6 PINS FOR CLOCK INPUTS
AND RESET
2 OTHER PINS (BKGD, TEST)
NOTE: MOST PINS HAVE
MULTIPLE FUNTIONS

13. ALTERNATE FUNCTIONS OF PORT PINS
PORTS A AND B - EXTERNAL ADDRESS/DATA BUS
PORT E - 8 BITS - CONTROL SIGNALS, MODE
SELECTION, INTERRUPT REQUESTS,
PORT T - 8 BITS - TIMER PINS
PORT S - 8 BITS - ASYNCHRONOUS SERIAL I/O (SCI)
PINS
PORT H - 8 BITS - SYNCHRONOUS SERIAL I/O (SPI)
PINS; INTERRUPT REQUESTS
PORT M - 8 BITS SPECIAL SERIAL I/O (BDLC, CAN)
PORT J - 4 BITS - INTERRUPT REQUESTS; CAN SIGNALS

14. MORE ALTERNATE FUNCTIONS OF PORT PINS
PORT P - 8 BITS - PULSE WIDTH MODULATION (PWM)
OUTPUTS; INTERRUPT REQUESTS
PORT K - 7 BITS - ADDRESS LINES A19-A14 FOR
EXPANDED (EXTERNAL ACCESS
MODE)
PORT AD0 - 8 BITS - INPUTS TO A/D CONVERTER 0
PORT AD1 - 8 BITS - INPUTS TO A/D CONVERTER 1

15. MC9SDP256B Block Diagram

16. Operating Modes Normal Single-Chip Mode • No External Addresses
No External Data Buses
Single Chip Stand Alone Mode
Port A – General Purpose I/O
Port B – General Purpose I/O
Selected by:
- BKGD =1, MODB = 0, MODA = 0
Operating Modes are Sensed at Reset

17. Operating Modes Normal Expanded Wide Mode
• Multiplexed 16-bit Address/16-bit Data Bus
Port A – High Address and Data Bits
Port B – Low Address and Data Bits
ADDR[7:0] and DATA[7:0]
Control Signals: R/W (from PE2)
ECLK (from PE4)
Selected by:
- BKGD =1, MODB = 1, MODA = 1

18. Operating Modes Normal Expanded Narrow Mode
• Multiplexed 16-bit Address/8-bit Data Bus
Port A – High Address and All 8 Data Bits- ADDR[15:8] and DATA[7:0]
Port B – Low Address
ADDR[7:0]
Control Signals: R/W (from PE2)
ECLK (from PE4)
Selected by:
- BKGD =1, MODB = 0, MODA = 1

20. MULTIPLEXED WIDE BUS
ADDR7 - ADDR0/ DATA7 - DATA0
PB7 - PB0
ADDR 15 - ADDR8/ DATA15 - DATA8
PA7 - PA0
PE2
R/W
(EXTERNAL BUS
CLOCK)
PE4
ECLK
LSTRB
PE3

21. MULTIPLEXED NARROW BUS
ADDR7 - ADDR0
PB7 - PB0
PA7 - PA0
ADDR 15 - ADDR8/ DATA7 - DATA0
PE2
R/W
PE4
ECLK

22. Access Type vs. Bus Control Pins
Table 12-5 Access Type vs. Bus Control Pins
/LSTRB A0 R/W Type of Access
bit read of an even address
bit read of an odd address
bit write of an even address
bit write of an odd address
bit read of an even address
XXX
bit write to an even address
XXX

23. Interface to 16-bit Data Bus
A17 .. A1
A17 .. A1
/cs1
cs2
/oe
/we
/cs1
cs2
/oe
/we
128K x 8
128K x 8
D15 .. D8
High Byte
D7 .. D0
Low Byte

24. ADDRESS LATCHES
MC9SDP256B12
ADDR7 - ADDR0
PB7 - PB0
CLK
ADDR 15 - ADDR8
PA7 - PA0
CLK
ECLK
PE4
ADDRESS LATCHED BY
ON CLK

25. Demultiplexed Address
ECLK
ADR2
ADR3
ADR4
ADR1
DAT2
DAT3
DAT3
DAT1
Demultiplexed
Address
ADR1
ADR2
ADR3
ADR4

26. PAGE ADDRESSING FOR EMULATION EXPANDED MODES
MC9SDP256B12
PK5 - PK0
XADDR19 - XADDR 14
PK7
ECS
(IF ECS = 0,
USE XADDR19 - XADDR 14,
ALONG WITH ADDR13 - ADDR0)
(IF ECS = 1, USE ONLY
ADDR15 - ADDR0)

27. ECLK WE R/W (WRITE) OE (READ)
GENERATION OF READ AND WRITE SIGNALS FOR MEMORY INTERFACING
ECLK WE
R/W
(WRITE) OE
(READ)

31. In the Normal Expanded Narrow Mode and the Normal Expanded Wide Mode, the Page Window Access Memory Region Can be Allocated Between External Memory and Internal Memory

32. The ECS Signal is activated in the Emulation Expanded Narrow Mode and the Emulation Expanded Wide Mode when the Microcontroller Tries to Access Memory Through the Page Access Window Which Would Have Been Accessed Internally if the Normal Expanded Narrow Mode or the Normal Expanded Wide Mode, Respectively, Had Been Used.