Sill Torres: Pipelined SAR Pipelined SAR with Comparator-Based Switch-Capacitor Residue Amplification Pedro Henrique Köhler Marra Pinto and Frank Sill Torres Universidade Federal de Minas Gerais (UFMG), Brazil Florianopolis, Feb. 29, 2016

Sill Torres: Pipelined SAR 2 Outline  Preliminaries  Pipelined Successive Approximation Register (PSAR) –General Architecture –Switch-Capacitor Residue Amplification –Zero-Crossing Detection  Results  Conclusion

Sill Torres: Pipelined SAR 3  Generation of internal analog signal V D/A with Digital Analog Converter (DAC)  Comparison of V D/A with input signal V in  Modification of V D/A by bits D 0 D 1..D N-1 until closest possible value to V in Preliminaries Successive Approximation Register V ref – reference voltage S&H – Sample and Hold circuit

Sill Torres: Pipelined SAR 4  Conversion separated in clocked stages  In each stage: subtraction of conversion result from stage input  Pipelined conversion of subsequent input signals Preliminaries Pipelined Converter

Sill Torres: Pipelined SAR 5 Preliminaries Pipelined Converter - Residue Amplification  Usually: OpAmp based  Common concepts: –Resistor network amplifier –Switched capacitor amplifier

Sill Torres: Pipelined SAR 6  ADC is based on combination of: –Successive Approximation Register (SAR)  Low power / low area  Slow –Pipelined Converter  Fast  High power / high area  Residue amplification –OpAmp => several problems in nanometer technologies (e.g., size, speed, robustness against variations) –Proposed solution based on  Comparator-based switched capacitor amplifier  Inverter-based zero-crossing detection Pipelined Successive Approximation Register Origin of Approach

Sill Torres: Pipelined SAR 7 Pipelined Successive Approximation Register Architecture

Sill Torres: Pipelined SAR 8 Pipelined Successive Approximation Register Successive Approximation Converter

Sill Torres: Pipelined SAR 9 Pipelined Successive Approximation Register Successive Approximation Converter

Sill Torres: Pipelined SAR 10 Pipelined Successive Approximation Register Switch-Capacitor Residue Amplification

Sill Torres: Pipelined SAR 11 Pipelined Successive Approximation Register Switch-Capacitor Residue Amplification - Architecture Inspired by Fiorenza, 2006, IEEE JSSC

Sill Torres: Pipelined SAR 12 Pipelined Successive Approximation Register Switch-Capacitor Residue Amplification - Architecture VF C1 C2 Storage capacitor CS ZCD Zero-Crossing Detection I

Sill Torres: Pipelined SAR 13 Pipelined Successive Approximation Register Switch-Capacitor Residue Amplification - Mode of Operation 1 st : VIN is sampled on C1 and C2 2 nd : Charge transfer phase + VOUT set to GND level 3 rd : Current source activated until VZCD crosses VCM

Sill Torres: Pipelined SAR 14 Pipelined Successive Approximation Register Zero-Crossing Detection - Architecture Inspired by Chao, 2013, ISSCC

Sill Torres: Pipelined SAR 15 Pipelined Successive Approximation Register Zero-Crossing Detection – Mode of Operation 1 st : Inverter shortened and VINV set to switch voltage of Inverter (VTH INV ) 2 nd : VIN (ramp) connected to inverter, inverter chain amplifies signal

Sill Torres: Pipelined SAR 16 Pipelined Successive Approximation Register Control Flow

Sill Torres: Pipelined SAR 17  Realized (on schematic level) in comercial 65nm technology  VDD = 1.2 V, Vref = 1 V, VCM = 0.5 V Results Overview f sample 4.4 MSPS DNL+0.45 / LSB 11 INL+0.43 / LSB 11 Power440 µW E/step [P/(f sample *2 11 )] 48.8 fJ/step [6] [5] [1] [4] [3] [2]

Sill Torres: Pipelined SAR 18 Results Integral Non-Linearity (INL)

Sill Torres: Pipelined SAR 19  Combination of two ADC concepts  Comparator-Based Switch-Capacitor Residue Amplification  Inverter-based zero-crossing detection  11 bit ADC implemented in 65 nm technology with low power and moderate speed Conclusion

Sill Torres: Pipelined SAR 20 Thank you! OptMA lab / ART