1. SAR ADC
Tao Chen

2. Successive-approximation Register (SAR) ADC
Chapter 17 Figure 05
Read chapter 17.2

3. Binary Search

4. Example timing diagram
At “convert start”, SHA grabs a sample and hold its value
Set DAC MSB to 1 as test bit, rest bits set to 0,
DAC output compared to sample held
If comparator output = 1, keep test bit as 1, else set test bit = 0
If test bit is LSB, reset “busy” and signal end of conversion
Else, move test bit to next lower bit, and set it to 1, generate DAC output
At end of conversion, DAC input code sent out as ADC output code

5. Charge redistribution implementation

6. Sampling Phase
Vin = 1.3
Vref = 5V

7. Conversion Phase 0
Vin = 1.3V
Vref = 5V

8. Conversion Phase 1
Vin = 1.3
Vref = 5V

9. Conversion Phase 2
Vin = 1.3
Vref = 5V 1

10. Conversion Phase 3
Vin = 1.3
Vref = 5V

11. For N-bit ADC
Conversion Phase 0 can be skipped
Non-overlapping Clock

12. Chapter 17 Figure 10

13. Segmented CDAC

14. Hybrid ADC

15. Hybrid ADC

16. Design Consideration Comparator: high speed, high resolution
Capacitor: matching & KT/C (area)
Switch: sampling time & conversion time

17. Project State-of-the-art ADCs R-string R2R Flash SAR Size R
CDAC (size C)
Segmentation
Decoder
Comparator
Switch
Encoder
SAR Logic
Buffer
Bubble rm
Clock/Timing
Power
ENOB
Speed
Area
State-of-the-art ADCs

18. Simulation Data converter simulation is very slow!
Histogram test, spectral test takes hours to days!
Server load is high at the end of the semester!
Server crashes very often !!
Start your project earlier !!!