Text-books 1. Digital System Design using VHDL by C.H. Roth. 2. Circuit Design with VHDL by Volnei A. Pedroni; Reference Book 1. VHDL Primer by J. Bhasker; Addison Wesley Longman Pub. 2. Introduction to Digital Systems by M. Ercegovec, T. Lang and L.J. Moreno; Wiley 3. VHDL: Analysis & Modeling of Digital Systems by Z. Navabi; MGH 4. VHDL Programming by Examples by Douglas L. Perry; TMH 5. VHDL by Douglas Perry 6. The Designer Guide to VHDL by P.J. Ashendem; Morgan Kaufmann Pub. 7. Digital System Design with VHDL by Mark Zwolinski; Prentice Hall Pub. 8. Digital Design Principles and Practices by John F. Wakerly, Prentice Hall (third Edition) 2001 includes Xilinx student edition).

 V- VHSIC  Very High Speed Integrated Circuit  H- Hardware  D- Description  L- Language

1. Public Standard, i.e. Human readable & machine readable. 2. Technology and Process Independent  Include technology via libraries 3. Supports a variety of design methodologies  Behavioral modeling  Dataflow or RTL (Register Transfer Language) Modeling  Structural or gate level modeling 4.Supports Design Exchange  VHDL Code can run on a variety of systems 5.Supports Design Reuse  Code “objects” can be used in multiple designs 6.Supports Design Hierarchy  Design can be implemented as interconnected sub modules 7.Supports Synchronous and Asynchronous Designs 8.Supports Design Simulation  Functional (unit delay)  Timing (“actual” delay) 9.Supports Design Synthesis  Hardware implementation of the design obtained directly from VHDL code. 10.Supports Design Documentation  Original purpose for VHDL – Department of Defense

Each VHDL Statements is terminated using a semicolon ; The language is case sensitive.

To include a comment in VHDL, use the comment operator -- This is a comment -- This is an example of a comment y <= 0; -- can occur at any point

To assign a value to a signal data object in VHDL, we use the signal assignment operator <= Example: y <= ‘1’; -- signal y is assigned the value ONE

 Entity Declaration  Describes external view of the design (e.g. I/O)  Architecture Body (AB)  Describes internal view of the design  Configuration Declaration  Package Declaration  Library Declaration  Package Body

Describes I/O of the model design. I/O Signals are called ports, through which it communicates. The syntax is: Entity NAME_OF_ENTITY is port(signal1,signal2,…..:mode type; signal3,signal4,…..:mode type); End NAME_OF_ENTITY ; Example: Half adder circuit. Entity HALF_ADDER is port(A, B:in BIT;-- BIT is a predefined language, “1” or “0” S, C: out BIT); End HALF_ADDER;  NAME_OF_ENTITY: user defined  signal_names: list of signals (both input and output)  mode: in, out, buffer, inout  type: boolean, integer, character, std_logic

Entity my_example is port( A, B, C: in std_logic; S: in std_logic_vector(1 downto 0); E, F: out std_logic; Y: out std_logic_vector(4 downto 0)); end my_example;

 A system (an entity) can be specified with different architectures Entity Architecture A Architecture B Architecture C Architecture D

 The architecture body contains the internal description of the design entity.  The VHDL specification states that a single design entity can contain multiple architecture bodies.  Each AB can be used to describe the design using a different level of abstraction. Architecture body can be build by using following modeling,  A set of interconnected components statements (to represent structure)  A set of concurrent assignment statement ( to represent dataflow)  A set of sequential assignment statement ( to represent behavior)  As any combination of above three.

 Architecture name of entity_name is internal signal and constant declarations Begin Concurrent statement 1; Concurrent statement 2; Concurrent statement 3; Concurrent statement 4; End architecture name;

 Structural architecture  implements the module as a composition of subsystems  contains  signal declarations, for internal interconnections  the entity ports are also treated as signals  component instances  instances of previously declared entity/architecture pairs  port maps in component instances  connect signals to component ports

 Full adder circuit using two half adder circuit. architecture STRUCTURAL of FULLADDER is signal S1, C1, C2 : bit; component HA port (I1, I2 : in bit; S, C : out bit); end component; component OR port (I1, I2 : in bit; X : out bit); end component; begin INST_HA1 : HA port map (I1 => B, I2 => C, S => S1, C => C1); INST_HA2 : HA port map (I1 => A, I2 => S1, S => SUM, C => C2); INST_OR : OR port map (I1 => C2, I2 => C1, X => CARRY); end STRUCTURAL; I 1 S HA1 I2 C I 1 S HA2 I2 C I 1 OR I2 x A C B CARRY SUM S1S1 C1C1 C2C2

architecture DEC_STRU of Decoder2x4 is component INV port(PIN: in BIT; POUT: out BIT); end component; component NAND port (D0, D1, D2: in BIT; DZ: out BIT); end component; signal ABAR, BBAR: BIT; begin INST_INV1: inv port map (A, ABAR); INST_INV2: inv port map (B, BBAR); INST_N0: NAND port map (ENABLE, ABAR, BBAR, Z(0)); INST_N1: NAND port map (ENABLE, ABAR, B, Z(0)); INST_N2: NAND port map (ENABLE, A, BBAR, Z(0)); INST_N3: NAND port map (ENABLE, A, B, Z(0)); End DEC_STRU;

-Flow of data through entity is expressed primarily through concurrent signal assignment statement. -Example architecture HA_DATAFLOW of HALF_ADDER is begin sum<= A xor B after 5ns;--ordering of signal is not important carry<= A and B after 5ns; end HA_DATAFLOW;

Architecture 2x4DEC_DATAFLOW of DECODER2x4 is signal ABAR, BBAR: BIT; begin ABAR<= not A; BBAR<= not B; Z(0)<=not (ABAR and BBAR and ENABLE); Z(1)<=not (ABAR and B and ENABLE); Z(2)<=not (A and BBAR and ENABLE); Z(3)<=not (A and B and ENABLE); end 2x4DEC_DATAFLOW;

Architecture Examples: Behavioral Description -It specifies the behavior of an entity as a set of statement that executes sequentially in the specific manner. -A process statement is concurrent statement that can appear in architecture body. -Variable is different from signal that it is always assigned a value instantaneously. -Hence the assignment operator used is different, - ‘ := ‘ compound symbol

Architecture 2x4DEC_BEHAVIOUR of DECODER2x4 is begin process (A, B, ENABLE) variable ABAR, BBAR: BIT; begin ABAR := not A; BBAR := not B; if ENABLE =‘1’ then Z(0)<= not (ABAR and BBAR); Z(1)<= not (ABAR and B); Z(2)<= not (A and BBAR); Z(3)<= not (A and B); else Z<= ‘111’; end if; end process; end 2x4DEC_BEHAVIOUR

entity FULL_ADDER is port (A, B, CIN: in BIT; SUM, COUT: out BIT); end FULL_ADDER; architecture FA_MIXED of FULL_ADDER is component XOR2 port (A, B: in BIT; Z: out BIT); end component; signal S1: BIT; begin X1: XOR2 port map (A, B, S1 ); - - structure. process (A, B, CIN) - - behavior. variable T1, T2, T3: BIT; begin T1 :=A and B; T2 := B and CIN; T3:=A and CIN; COUT <= T1 or T2 or T3; end process; SUM <= S1 xor CIN; - - dataflow. end FA_M!XED; Architecture: Mixed Style of Modeling

- It is used to select one of the possibly many architecture bodies that an entity have. - There are no behavioral or simulation semantics associated with a configuration declaration. -Syntax: - Example:

-It is used to store a set of commands declarations, such as component, type, procedure & function, imported from other design. -Example: - -- This is library cause* This is use cause**. -* The library cause declares the designed library. - ** The use cause imports all the declarations within the package STD_LOGIC_1164

-It is used to store the definitions of function & procedures which is already declared in package declaration. -It is also associated with architecture body & entity declared. - Name of package body must be same as that of the associated package declaration. -Syntax:

Basic IdentifiersExtended Identifiers 1) Sequence of 1 or more characters. 2) Legal characters are, Upper case letters (A…Z), Lower case letters (a….z), A digit (0,1,…..9) or underscore ( _ ). 3) First char. In a basic identifier must be a letter & last char. May not be an underscore. 4) Examples: - SelectSignal - Constant_1_A - RAM_Address_1 1) Sequence of characters written between two back slashes. 2) Legal characters are, characters like,., and $. 3) Within an extended identifiers, lower case, upper case letters. 4) Examples: - - \process\ - \TEST\ - \----\\-----\

 VHDL is an Object Oriented Programming (OOP) Language.  Objects can have values, attributes and methods.  Primarily used VHDL data objects are: - Signals - Constants - Variables - File

 Signals are data objects in which the value of the object can be changed.  It can hold a list of values.  A Signal has three properties attached to it: type, value and time.  There is an implied or explicit delay between the signal assignment and when the signal is updated.  Signals is use to represent nets (i.e. wires) in our circuits.  They can be implemented in hardware.  Signals are defined in port statements and architecture declaration blocks. Syntax: signal signal_name: type := value; Examples: - signal CLOCK:BIT; - signal P: STD_LOGIC_VECTOR( 7 downto 0); - signal Delay: TIME:= 10ns;

 Constants are data objects in which the value of the object cannot be changed.  As the name suggested it’s a constant.  It holds a signal value of a given type.  They are defined within an architecture or process declaration block.  They cannot be implemented in hardware. - Syntax: constant constant_name: type := value; - Example: constant RISE_TIME: TIME:= 10ns; constant No_of_Inputs: INTEGER;

 Variables are data objects in which the value of the object can be changed.  This change occurs instantaneously.  A variable has only two properties attached to it type and value.  Variables can only be defined within a process declaration block.  They cannot be implemented in hardware.  Different value can be assign to variable at different times using variable assignment statement. - Syntax: variable variable_name: type := value; - Example: variable Status_Control: BIT_VECTOR (10 downto 0); variable SUM: INTEGER range 0 to 100:=10;

 It contains a sequence of values.  Values can read or written to the file using read procedure & write procedure respectively.  A file is used to model a file in the host environment.  For a file, the object declaration may specify information on how to open the file. - Syntax: file file_name : file_type_name [[open mode] is srring_expression]; - Example: file Vectors : BIT_FILE is “/user/home/add.vec”; file STIMULES: TEXT open READ_MODE is “/user/home/add.vec”; file BIT_FILE is file of BIT_VECTOR;

 A Signal has three properties attached to it: type, value and time. while a variable has only two properties attached to it type and value.  Use signals as channels of communication between concurrent statement. In non-synthesizeable models (contains real, time, events), avoid using signals to describe storage elements, so variable are used.  Signals occupy about two orders of magnitude more storage than variable during simulation.  Signals also cost a performance penalty due to the simulation overhead necessary to maintain the data structures representing signals. Signals follow the ‘event scheduling’ where variable don’t. 31

-Every data object is holding a value which belongs to a set of value specified by a type declaration. -Therefore type declaration which exist in the language is categories as, 1)Scalar Type value appearing is in sequential order. 2) Composite It’s a composition of elements of single or different type. 3)Access Similar to the pointer, which provides access to object. 4)File It provides access to object that contain a sequence of values of a given type.

Further sub divided as, Discrete type Numeric Type

 Enumeration Type – It’s a discrete literal type defines a type which is a set of user-defined values, which consist of identifiers & character literals.  type MY_VAL is (‘0’, ‘1’, ‘2’, ‘A’);  type LOGIC is (AND, OR, NOT, XOR);  type Dig_IP_State is (‘0’, ‘1’);  Integer Type – It’s a discrete or integer literal type values which comes under a specified integer range between - ( ) to + ( ).  type REG_SIZE is range 0 to 31;  subtype WORD is REG_SIZE range 15 downto 0; The integer literals are also defined as, 6E2 refers the decimal value as, 6 * (10 2 ) 98_71_28 no impact of ‘_’ sign hence similar to as,

Floating Point Type – It’s a set of real number literal type. type TTL_Voltage is range to - 1.4; type Input is range 0.0 to 9.9; Floating point literals are differs from integer literals by presence of a dot (.) Hence 0 is integer literal & 0.0 is floating point literal. The exponential forms are, 62.3E+2 represents, 62.3 * (10 2 ) 62.3E-2 represents, 62.3 * ( ) Based Literals having base between 2 & 16 are defined as, 2#101_101_000# represents ( ) 2 = (360) in decimal 16#FA# represents (FA) 16 = ( ) 2 = (250) in decimal Physical Type – represent measurement of some physical quantity like time, voltage, or current, expressed as integer multiplies of a base unit. type Current is range 0 to 1E-9 units nA;-- Base unit is nano ampere uA = 1000 nA;-- micro ampere mA = 1000 uA;-- milli ampere Amp = 1000 mA;-- ampere End units; Scalar Type continue….

 Array Types – collection of values all belonging to a single type BIT_VECTOR and STRING are pre-defined one-dimensional array types  type DATA_BYTE is array (0 to 7) of BIT;  type MEMORY is array (0 to 127) of DATA_BYTE;  Record Types – collection of values that may belong to different types  Similar to a “struct” declaration in C type MODULE is record SUM:BIT_VECTOR(0 to 7); COUT:BIT; end record;

3) Access type – - It’s a pointer to a dynamically allocated object of some other type. Similar to pointer in C.  type FIFO is array (0 to 7) of BIT;  type FIFO is array (0 to 7, 0 to 63) of BIT;  type MEMORY is array (0 to 127) of DATA_BYTE; Object of access type can be referred as, ii) obj.ptr.all Which access the entire object pointed by obj.ptr. ii) array-obj-ptr Access the specified array element. iii) Record-obj.ptr.element Access the specified record element.

4) File type – -Object of file types represent files in the host environment. Syntax – type file_type_name is file of type_name; Example – type Vectors is file of BIT_VECTORS; type Name is file of String;

Proced ance Operator ClassOperators Low High Logical (7) andornandnorxorxnornot Relational (6) =/=<<=>>= Shift (6) sllsrlslasrarolror Add (3) +-& Multiply (3) * (multiplication/division) Mod (modulud) Rem (reminder) Miscellaneous (2) abs (Absolute) ** (exponential) * not is called as unary logical operator.

operators.pdf