Lecture 14 State Machines II Topics State Machine Design Resolution with Text Design with D flip-flops Design with JK Readings: Chapter 7 November 11, 2015 CSCE 211 Digital Design

– 2 – CSCE 211H Fall 2014 Overview Last Time State machine construction HW $.50 coke machine with no changeNew  State machine construction again (text notation) Next Time: Test 2 : Nov 16 th next Monday

– 3 – CSCE 211H Fall 2014 P = (S + Q)´ Q = (R + P)´

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– 7 – CSCE 211H Fall 2014 Continuing Examples (CE) CE7. A Mealy system with one input x and one output z such that z = 1 at a clock time iff x is currently 1 and was also 1 at the previous two clock times. CE8. A Moore system with one input x and one output z, the output of which is 1 iff three consecutive 0 inputs occurred more recently than three consecutive 1 inputs. CE9. A system with no inputs and three outputs, that represent a number from 0 to 7, such that the output cycles through the sequence and repeat on consecutive clock inputs. CE10. A system with two inputs, x 1 and x 2, and three outputs, z 1, z 2, and z 3, that represent a number from 0 to 7, such that the output counts up if x 1 = 0 and down if x 1 = 1, and recycles if x 2 = 0 and saturates if x 2 = 1. Thus, the following output sequences might be seen x 1 = 0, x 2 = 0: … x 1 = 0, x 2 = 1: … x 1 = 1, x 2 = 0: … x 1 = 1, x 2 = 1: … (Of course, x 1, and x 2 may change at some point so that the output would switch from one sequence to another.)

– 8 – CSCE 211H Fall 2014 Step 1 : From a word description, determine what needs to be stored in memory, that is, what are the possible states. Step 2 : If necessary, code the inputs and outputs in binary. Step 3 : Derive a state table or state diagram to describe the behavior of the system. Step 4 : Use state reduction techniques (see Chapter 7) to find a state table that produces the same input/output behavior, but has fewer states. Step 5 : Choose a state assignment, that is, code the states in binary. Step 6 : Choose a flip flop type and derive the flip flop input maps or tables. Step 7 : Produce the logic equation and draw a block diagram (as in the case of combinational systems).

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– 11 – CSCE 211H Fall 2014 D 1 = x q 2 + x q 1 D 2 = x q´ 2 + x q 1

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– 14 – CSCE 211H Fall 2014 J 1 = xq 2 K 1 = x´ z = q 1 q 2 J 2 = x K 2 = x´ + q´ 1

– 15 – CSCE 211H Fall 2014 S 1 = xq 2 R 1 = x´ z = q 1 q 2 S 2 = xq´ 2 R 2 = x´ + q´ 1 q 2

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– 17 – CSCE 211H Fall 2014 T 1 = x´q 1 + xq´ 1 q 2 T 2 = x´q 2 + xq´ 2 + xq´ 1 q 2 z = q 1 q 2

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– 23 – CSCE 211H Fall 2014 J 1 = 1 K 1 = xq 2 J 2 = x´ K 2 = x´ z = x´ + q 1 q 2 D 1 = x´ + q´ 1 + q´ 2 D 2 = xq´ 2 + xq´ 2

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– 25 – CSCE 211H Fall 2014 D A = xAC´ + xBC D B = x´A + x´B + x´C D C = x´A + x´B + x´C´ + AC´ z = A + BC J D = K D = CBA J C = K C = BA J B = K B = A J A = K A = 1

– 26 – CSCE 211H Fall 2014 J A = K A = 1 J B = K B = x´A + xA´ J C = K C = x´BA + xB´A´

– 27 – CSCE 211H Fall , 3, 2, 4, 1, 5, 7, and repeat

– 28 – CSCE 211H Fall 2014 D 1 = q´ 2 q 3 + q 2 q´ 3 D 2 = q´ 1 q´ 2 q´ 3 + q´ 1 q 2 q 3 + q 1 q´ 2 q 3 D 3 = q´ 2

– 29 – CSCE 211H Fall 2014 q 1 = 1, q 2 = 1, and q 3 = 0 D 1 = q´ 2 q 3 + q 2 q´ 3 = = 1 D 2 = q´ 1 q´ 2 q´ 3 + q´ 1 q 2 q 3 + q 1 q´ 2 q 3 = = 0 D 3 = q´ 2 = 0

– 30 – CSCE 211H Fall 2014 CE6. A system with one input x and one output z such that z = 1 iff x has been 1 for at least three consecutive clock times.

– 31 – CSCE 211H Fall 2014 A none, that is, the last input was 0 B one C two D three or more

– 32 – CSCE 211H Fall 2014 CE7. A system with one input x and one output z such that z = 1 at a clock time iff x is currently 1 and was also 1 at the previous two clock times. CE7#. A Mealy system with one input x and one output z such that z = 1 iff x has been 1 for three consecutive clock times.

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– 34 – CSCE 211H Fall 2014 A none, that is, the last input was 0 B one C two or more

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– 36 – CSCE 211H Fall 2014 Design a Mealy system with one input x and one output z such that z = 1 iff x has been 1 for exactly three consecutive clock times. A sample input/output trace for such a system is x z ↑ ↑ A none, that is, the last input was 0 B one 1 in a row C two 1’s in a row D three 1’s in a row E too many (more than 3) 1’s in a row

– 37 – CSCE 211H Fall 2014 Design a Moore system with one input, x, and one output z such that z = 1 iff x has been 1 for exactly three consecutive clock times. x z

– 38 – CSCE 211H Fall 2014 CE8. Design a Moore system whose output is 1 iff three consecutive 0 inputs occurred more recently than three consecutive 1 inputs. A sample input/output trace for such a system is x z? ? ?

– 39 – CSCE 211H Fall 2014 CE11. Design a Moore model bus controller that receives requests on separate lines, R 0 to R 3, from four devices desiring to use the bus. It has four outputs, G 0 to G 3, only one of which is 1, indicating which device is granted control of the bus for that clock period. The low number device has the highest priority, if more than one device requests the bus at the same time. We look at both interrupting controllers (where a high priority device can preempt the bus) and one where a device keeps control of the bus once it gets it until it no longer needs it. The bus controller has five states: A: idle, no device is using the bus B: device 0 is using the bus C: device 1 is using the bus D: device 2 is using the bus E: device 3 is using the bus

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– 43 – CSCE 211H Fall 2014 Read Only Memory Functionality

– 44 – CSCE 211H Fall Input 4-Output ROM 3x8 decoder A0 A1 A2 A0 OR D0 D1 D2 D3

– 45 – CSCE 211H Fall 2014 Construction of a 2 x n ROM Zap some connections during construction Denoted “x” 2x4 decoder A0 A1 d0 d1 d2 d3 … Y0Y1Y2Yn-1

– 46 – CSCE 211H Fall x4 Decoder with Output-Polarity Control Figure 9-2

– 47 – CSCE 211H Fall 2014 Implementing Arbitrary Boolean functions with ROMs

– 48 – CSCE 211H Fall 2014 Multipliers in ROM Figure 9-4

– 49 – CSCE 211H Fall 2014 Logic Diagram of 8x4 diode ROM x 74LS138 =1-OF-8 DECODER/ DEMULTIPLEXER

– 50 – CSCE 211H Fall 2014 Two-Dimensional Decoding

– 51 – CSCE 211H Fall 2014 Field Programmable Gate Arrays Xilinx Spartan-3 FPGA family. Download circuits onto the chip FPGA Field Programmable Gate array Spartan-3 FPGAs with 1 million system gates for under $12.00

– 52 – CSCE 211H Fall 2014 Xilinx FPGA

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