1. Chapter 7
The Design of
Sequential Systems

2. Five additional Continuing Examples(CE)
Chapter 7 The Design of Sequential Systems
Five additional Continuing Examples(CE)
CE7. A Mealy system with one input x and one output z such that z = 1 at a clock time iff x is currently 1 and was also 1 at the previous two clock times.
CE8. A Moore system with one input x and one output z, the output of which is 1 iff three consecutive 0 inputs occurred more recently than three consecutive 1 inputs.
CE9. A Moore system with no inputs and three outputs, that represent a number from 0 to 7, such that the outputs cycle through the sequence and repeat on consecutive clock inputs.

3. Chapter 7 The Design of Sequential Systems
CE10. A Moore system with two inputs, x1 and x2, and three outputs, z1, z2, and z3, that represent a number from 0 to 7, such that the output counts up if x1 = 0 and down if x1 = 1, and recycles if x2 = 0 and saturates if x2 = 1. Thus, the following output sequences might be seen
x1 = 0, x2 = 0: …
x1 = 0, x2 = 1: …
x1 = 1, x2 = 0: …
x1 = 1, x2 = 1: …
CE11. A bus controller that receives requests on separate lines, R0 to R3, from four devices desiring to use the bus. It has four outputs, G0 to G3, only one of which is 1, indicating which device is granted control of the bus for that clock period

4. Step 1 : From a word description, determine what to be stored in
Chapter 7 The Design of Sequential Systems
For Larger system,
Step 1 : From a word description, determine what to be stored in
memory, that is, what are the possible states.
Step 2 : If necessary, code the inputs and outputs in binary.
Step 3 : Derive a state table or state diagram to describe the behavior
of the system.
Step 4 : Use state reduction techniques to find a state table that
produces the same input/output behavior, but has fewer states.
Step 5 : Choose a state assignment, that is, code the states in binary.
Step 6 : Choose a flip flop type and derive the flip flop input maps or
tables.
Step 7 : Produce the logic equation and draw a block diagram (as in the
case of combinational systems).

5. (a) (b) (c) Chapter 7 The Design of Sequential Systems P 328 q q1 q2 AB 1 C D q q1 q2 A B 1 C D q q1 q2 A B 1 C D
(a)
(b)
(c)
P 328

6. The second half of the table corresponds to x = 1.
Chapter 7 The Design of Sequential Systems q x q1 q2
q1*
q2* A B 1 C D
The first half of the design truth table corresponds to the first column of
the state table(x = 0).
The next state is 0 0 for the first four rows, since each of the states go to
state A on a 0 input.
The second half of the table corresponds to x = 1.
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7. Chapter 7 The Design of Sequential Systems
6 - 7
For a Moore system, q q1 q2 z A B 1 C D
A separate table for the output, since it depends only on the two state
variables.
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8. Chapter 7 The Design of Sequential Systems
6 - 8
The equations,
q1* = xq2 + xq1
q2* = xq’2 + xq1
z = q1q2
This SOP solution requires 4 two-input AND gates and 2 two-input OR gates.
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9. Example 7.1 Design truth table:
Chapter 7 The Design of Sequential Systems
6 - 9
Example 7.1
Design truth table: x q1 q2
q1*
q2* A D 1 C B q q1 q2 z A D 1 C B
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10. The resulting maps: The resulting maps: q1* = xq’1q’2 + xq1q2
Chapter 7 The Design of Sequential Systems
6 - 10
The resulting maps: 1 00 01 11 10
q1 *
q1 q2 x
q2*
The resulting maps:
q1* = xq’1q’2 + xq1q2
q2* = xq’1 + xq’2
z = q’1q2
This implementation requires an extra gate and three extra gate inputs.
P 330

11. 7.1 FLIP FLOP DESIGN TECHNIQUES
Chapter 7 The Design of Sequential Systems
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7.1 FLIP FLOP DESIGN TECHNIQUES
The flip flop design table is most readily obtained from the state diagram. q q*
Input(s) 1
For each line of the truth table equivalent of the state table, and for each
flip flop.
Its present value and the desired next state. 1 D
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12. 7.1 FLIP FLOP DESIGN TECHNIQUES
Chapter 7 The Design of Sequential Systems
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7.1 FLIP FLOP DESIGN TECHNIQUES
The diagram indicates that if the flip flop is in state 0 and the desired
next state is also 0, the only path is D = 0. q q* D 1
When the D flip flop.
Don’t separate columns in the truth table for D1 and D2.
They are identical to the q1* and q2* columns.
D1 = xq2 + xq1
D2 = xq’2 + xq1
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13. 7.1 FLIP FLOP DESIGN TECHNIQUES
Chapter 7 The Design of Sequential Systems
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7.1 FLIP FLOP DESIGN TECHNIQUES
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14. 7.1 FLIP FLOP DESIGN TECHNIQUES
Chapter 7 The Design of Sequential Systems
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7.1 FLIP FLOP DESIGN TECHNIQUES
Repeat the process for the JK flip flop. 1 JK 00 01 10 11
To go from state 0 to state 0.
Two choices : J = 0 and K = 0, or J = 0 and K = 1 (J must be 0 and it does not matter what K is – K is a don’t care.) q q* J K X 1
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15. 7.1 FLIP FLOP DESIGN TECHNIQUES
Chapter 7 The Design of Sequential Systems
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7.1 FLIP FLOP DESIGN TECHNIQUES x q1 q2
q1*
q2* J1 K1 J2 K2 X 1
The truth table for the design requires four more columns for the four flip
flop inputs.
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16. 7.1 FLIP FLOP DESIGN TECHNIQUES
Chapter 7 The Design of Sequential Systems
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7.1 FLIP FLOP DESIGN TECHNIQUES 1 00 01 11 10 J1
q1 q2 x X J2 J3 J4
The flip flop input equations are
J1 = xq2 K1 = x’ z = q1q2
J2 = x K2 = x’ + q’1
This requires just 2 two-input AND gates, 1 two-input OR gate, and a NOT
for x’, by far the least expensive solution.
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17. 7.1 FLIP FLOP DESIGN TECHNIQUES
Chapter 7 The Design of Sequential Systems
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7.1 FLIP FLOP DESIGN TECHNIQUES
Example 7.2
The state diagram for the SR flip flop. 1 SR 00 01 10
1 0
0 1
The resulting SR flip flop design table is q1 q* S R X 1
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18. 7.1 FLIP FLOP DESIGN TECHNIQUES
Chapter 7 The Design of Sequential Systems
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7.1 FLIP FLOP DESIGN TECHNIQUES
Following the same technique as for JK flip flop. x q1 q2
q1*
q2* S1 R1 S2 R2 X 1
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19. 7.1 FLIP FLOP DESIGN TECHNIQUES
Chapter 7 The Design of Sequential Systems
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7.1 FLIP FLOP DESIGN TECHNIQUES 1 00 01 11 10 S1
q1 q2 x X R1 S2 R2
The input equations are
S1 = xq2 R1 = x’ z = q1q2
S2 = xq’2 R2 = x’ + q’1q2
This requires 4 two-input AND gates, 1 two-input OR gate, and 1 NOT gate for x’.
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20. 7.1 FLIP FLOP DESIGN TECHNIQUES
Chapter 7 The Design of Sequential Systems
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7.1 FLIP FLOP DESIGN TECHNIQUES
Example 7.3
The state diagram for the T flip flop. 1 T
There is only one way to get from any state to any other state. q1 q* T 1
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21. 7.1 FLIP FLOP DESIGN TECHNIQUES
Chapter 7 The Design of Sequential Systems
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7.1 FLIP FLOP DESIGN TECHNIQUES
The truth table for the system design becomes x q1 q2
q1*
q2* T1 T2 1
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22. 7.1 FLIP FLOP DESIGN TECHNIQUES
Chapter 7 The Design of Sequential Systems
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7.1 FLIP FLOP DESIGN TECHNIQUES x x 1 1
q1 q2
q1 q2 00 00 1 01 1 01 1 1 11 1 11 1 10 1 10 1 T1 T2
The input equations are
T1 = x’q1 + xq’1q2
T2 = x’q2 + xq’2 + x q’1q2
z = q1q2
This requires 4 two-input AND gates, 1 three-input AND gate, 1 two-input
and 1 three-input OR gate, and 1 NOT gate for x.
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23. 7.1 FLIP FLOP DESIGN TECHNIQUES
Chapter 7 The Design of Sequential Systems
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7.1 FLIP FLOP DESIGN TECHNIQUES
The JK solution never requires more logic than either the SR or the T.
All of the X’s in the SR solution are also X’s on the JK maps.
The JK maps have additional don’t care.
The JK flip flop would behave like a T.
The relationship between the D and JK design is not quite so clear.
The input equations for any flip flop are derived from the q and q*
columns for that flip flop.
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24. 7.1 FLIP FLOP DESIGN TECHNIQUES
Chapter 7 The Design of Sequential Systems
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7.1 FLIP FLOP DESIGN TECHNIQUES
The shaded columns on the q1* map, together with the JK flip flop
design table are used, row by row, to produce the shaded columns on the
J1 and K1 maps.
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25. 7.1 FLIP FLOP DESIGN TECHNIQUES
Chapter 7 The Design of Sequential Systems
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7.1 FLIP FLOP DESIGN TECHNIQUES
To get the second column of the J1 and K1 maps.
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26. 7.1 FLIP FLOP DESIGN TECHNIQUES
Chapter 7 The Design of Sequential Systems
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7.1 FLIP FLOP DESIGN TECHNIQUES
To find J and K for flip flop q2,
This same technique can be used with the other type of flip flops.
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27. 7.1 FLIP FLOP DESIGN TECHNIQUES
Chapter 7 The Design of Sequential Systems
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7.1 FLIP FLOP DESIGN TECHNIQUES
The quick method for JK flip flop design takes advantage of a property
of JK flip flops. 1 00 01 11 10 J1
q1 q2 x X K1 J2 K2
x q2
x’ q2’
x q1’
x’ q1’
x’ q2
x q1
x’ q1
Half of each map contains don’t cares.
Each of the 1’s on the map has a don’t care eliminate the variable involved.
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28. 7.1 FLIP FLOP DESIGN TECHNIQUES
Chapter 7 The Design of Sequential Systems
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7.1 FLIP FLOP DESIGN TECHNIQUES
Advantage of this property by utilizing the equation.
q* = Jq’ + K’q
when q = 0,
q* = J ∙ 1 + K’ ∙ 0 = J
when q = 1,
q* = J ∙ 0 + K’ ∙ 1 = K’
The part of the map of q* for which that variable is 0 is the map for J
and the part for which that variable is 1 is the map for K’

29. 7.1 FLIP FLOP DESIGN TECHNIQUES
Chapter 7 The Design of Sequential Systems
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7.1 FLIP FLOP DESIGN TECHNIQUES
The three variable map has been reduced to 2 two-variable maps, one
for J and the other for K’.
The variable q1 has been eliminated; that was used to choose the section
of the original map.
J1 = xq2 K’1 = x or K1 = x’
Be careful in using the map for K’1; the two rows are reversed, that is,
the q2 = 1 row is on the top.
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30. 7.1 FLIP FLOP DESIGN TECHNIQUES
Chapter 7 The Design of Sequential Systems
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7.1 FLIP FLOP DESIGN TECHNIQUES
The q2 = 0 portion of the map consists of the first and last rows
The q2 = 1 portion is made up of the middle two rows.
The other methods,
J2 = x K2 = x’ + q’1
It is really only necessary to plot maps of q* for each variable.
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31. 7.1 FLIP FLOP DESIGN TECHNIQUES
Chapter 7 The Design of Sequential Systems
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7.1 FLIP FLOP DESIGN TECHNIQUES
Example 7.4
The state table and the state assignment. q* z q
x = 0
x = 1 A B C 1 q q1 q2 A 1 B C
Following truth table (including a column with the state name) x q1 q2
q1*
q2* z - X C 1 B A
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32. 7.1 FLIP FLOP DESIGN TECHNIQUES
Chapter 7 The Design of Sequential Systems
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7.1 FLIP FLOP DESIGN TECHNIQUES
The resulting maps for the output and for D flip flop inputs follow. 1 00 01 11 10 z
q1 q2 x X
q1 *
q2 *
The resulting equation
z = x’ + q1q2
D1 = x’ + q’1 + q’2
D2 = xq’2 + x’q2
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33. 7.1 FLIP FLOP DESIGN TECHNIQUES
Chapter 7 The Design of Sequential Systems
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7.1 FLIP FLOP DESIGN TECHNIQUES x q1 q2
q1*
q2* z J1 K1 K2 - X C 1 B A
The equations for the flip flop inputs follow.
J1 = 1 K1 = xq2
J2 = x’ K2 = x’
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34. 7.1 FLIP FLOP DESIGN TECHNIQUES
Chapter 7 The Design of Sequential Systems
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7.1 FLIP FLOP DESIGN TECHNIQUES
Example 7.5
One larger example q* q
x = 0
x = 1 z S1 S2 S3 S4 S5 1 S6
The first issue is to make a state assignment.
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35. 7.1 FLIP FLOP DESIGN TECHNIQUES
Chapter 7 The Design of Sequential Systems
6 - 35
7.1 FLIP FLOP DESIGN TECHNIQUES q A B C S1 S2 1 S3 S4 S5 S6 q A B C S1 S2 1 S3 S4 S5 S6
The first assignment just uses the first six binary number.
The second assignment uses an assignment meant to reduce the
combinational logic.
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36. 7.1 FLIP FLOP DESIGN TECHNIQUES
Chapter 7 The Design of Sequential Systems
6 - 36
7.1 FLIP FLOP DESIGN TECHNIQUES
The left half of the map corresponds to x = 0, and the right half to x =1.
Since S1 goes to S2 when x = 0, the upper left square for the maps become 0, 0,
and 1.
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37. 7.1 FLIP FLOP DESIGN TECHNIQUES
Chapter 7 The Design of Sequential Systems
6 - 37
7.1 FLIP FLOP DESIGN TECHNIQUES
DA = xAC’ + xBC
DB = x’A + x’B + x’C
DC = x’A + x’B + x’C’ + AC’
z = A + BC
P 343

38. 7.1 FLIP FLOP DESIGN TECHNIQUES
Chapter 7 The Design of Sequential Systems
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7.1 FLIP FLOP DESIGN TECHNIQUES
Using AND and OR gates, this requires 13 gates with 30 inputs.
To implement this with JK flip flops,
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39. 7.1 FLIP FLOP DESIGN TECHNIQUES
Chapter 7 The Design of Sequential Systems
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7.1 FLIP FLOP DESIGN TECHNIQUES
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40. 7.1 FLIP FLOP DESIGN TECHNIQUES
Chapter 7 The Design of Sequential Systems
6 - 40
7.1 FLIP FLOP DESIGN TECHNIQUES
The map for JA has don’t cares in the two columns for which A is 1 and the map for KA has X’s in the two columns for which A is 0.
Rows of don’t cares are seen in the maps for B* and C*.
JA = xBC JB = x’A + x’C JC = x’ + A
KA = x’ + C KB = x KC = x + A’B’
The output does not depend on the flip flop type.
z = A + BC
This requires 11 gates and 22 inputs. A B C
Gates
Inputs D JK 13 28 29 12 27 25 26 30 11 22
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41. 7.1 FLIP FLOP DESIGN TECHNIQUES
Chapter 7 The Design of Sequential Systems
6 - 41
7.1 FLIP FLOP DESIGN TECHNIQUES
The first eight rows are completed for the output column z, since z is not a function of the input x. x A B C z A* B* C* JA KB JB JC KC S1 1 X - S6 S5 S3 S2 S4
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42. 7.1 FLIP FLOP DESIGN TECHNIQUES
Chapter 7 The Design of Sequential Systems
6 - 42
7.1 FLIP FLOP DESIGN TECHNIQUES
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43. 7.1 FLIP FLOP DESIGN TECHNIQUES
Chapter 7 The Design of Sequential Systems
6 - 43
7.1 FLIP FLOP DESIGN TECHNIQUES
DA = x’
DB = x’B + BC + x’AC’
DC = AB + x’C’ + {x’B or x’A’}
This requires a total of 9 gates with 20 inputs.
The equations of JK version.
JA = x’ KA = x
JB = x’AC’ KB = xC’
JC = x’ KC = B’ + xA’
x = B
This requires 5 gates with 10 inputs, significantly better than the D solution.

44. 7.2 THE DESIGN OF SYNCHRONOUS COUNTERS
Chapter 7 The Design of Sequential Systems
6 - 44
7.2 THE DESIGN OF SYNCHRONOUS COUNTERS
Counters
Asynchronous counters : those that do not require a clock input.
Most counters are devices with no data input, that go through a fixed sequence of states on successive clocks.
The output is often just the state of the system, that is, the contents of all of the flip flops.
4-bit binary counter : one with four flip flops that cycles through the sequence
0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 0, 1, . . .
There are really no new techniques required for this design.
The state table and the truth table are the same.
The flip flops are labeled D, C, B, and A, which is the common practice.

45. 7.2 THE DESIGN OF SYNCHRONOUS COUNTERS
Chapter 7 The Design of Sequential Systems
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7.2 THE DESIGN OF SYNCHRONOUS COUNTERS D C B A D*
C * B* A* 1
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46. 7.2 THE DESIGN OF SYNCHRONOUS COUNTERS
Chapter 7 The Design of Sequential Systems
6 - 46
7.2 THE DESIGN OF SYNCHRONOUS COUNTERS
DD = DC’ + DB’ + DA’ + D’CBA
DC = CB’ + CA’ + C’BA
DB = B’A + BA’
DA = A’
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47. 7.2 THE DESIGN OF SYNCHRONOUS COUNTERS
Chapter 7 The Design of Sequential Systems
6 - 47
7.2 THE DESIGN OF SYNCHRONOUS COUNTERS
This solution would require 12 gates with 30 gate inputs.
Exclusive-OR gates available.
DD = D(C’ + B’ + A’) + D’CBA = D(CBA)’ + D’(CBA)
= D CBA
DC = C(B’ + A’) + C’BA = C(BA)’ + C’(BA) = C BA
DB = B’A + BA’ = B A
DA = A’
This would only require two AND gates and three Exclusive-OR gates.
JK design,
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48. 7.2 THE DESIGN OF SYNCHRONOUS COUNTERS
Chapter 7 The Design of Sequential Systems
6 - 48
7.2 THE DESIGN OF SYNCHRONOUS COUNTERS
This produces the equations
JD = KD = CBA
JC = KC = BA
JB = KB = A
JA = KA = 1
Extend the design to 5 flip flops, counting to 31 by adding flip flop E with inputs
JE = KE = DCBA
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49. 7.2 THE DESIGN OF SYNCHRONOUS COUNTERS
Chapter 7 The Design of Sequential Systems
6 - 49
7.2 THE DESIGN OF SYNCHRONOUS COUNTERS
Up/down counter : one that can count in either direction, depending on a
control input.
Control input x : counter counts up when x = 0 and down when x = 1. x C B A
C * B* A* 1
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50. 7.2 THE DESIGN OF SYNCHRONOUS COUNTERS
Chapter 7 The Design of Sequential Systems
6 - 50
7.2 THE DESIGN OF SYNCHRONOUS COUNTERS
JA = KA = 1
JB = KB = x’A + xA’
JC = KC = x’BA + xB’A’
Just as in the case of the 4- and 5-bit up counters, this pattern continues, yielding
JD = KD = x’CBA + x C’B’A’
JE = KE = x’DCBA + xD’C’B’A’
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51. 7.2 THE DESIGN OF SYNCHRONOUS COUNTERS
Chapter 7 The Design of Sequential Systems
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7.2 THE DESIGN OF SYNCHRONOUS COUNTERS
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52. 7.2 THE DESIGN OF SYNCHRONOUS COUNTERS
Chapter 7 The Design of Sequential Systems
6 - 52
7.2 THE DESIGN OF SYNCHRONOUS COUNTERS
Example 7.6
Design a counter that goes through some sequence of states that are not in numeric order
0, 3, 2, 4, 1, 5, 7, and repeat
The cycle is 7 states; it never goes through state 6. q1 q2 q3
q1*
q2*
q3* 1 X
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53. 7.2 THE DESIGN OF SYNCHRONOUS COUNTERS
Chapter 7 The Design of Sequential Systems
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7.2 THE DESIGN OF SYNCHRONOUS COUNTERS
The table is repeated below with columns for inputs to SR flip flops; use the quick method for JK flip flops. q1 q2 q3
q1*
q2*
q3* S1 R1 S2 R2 S3 R3 1 X
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54. 7.2 THE DESIGN OF SYNCHRONOUS COUNTERS
Chapter 7 The Design of Sequential Systems
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7.2 THE DESIGN OF SYNCHRONOUS COUNTERS
For D flip flops
Use the q1*, q2*, q3* columns.
D1 = q’2q3 + q2q’3
D2 = q’1q’2q’3 + q’1q2q3 + q1q’2q3
D3 = q’2
This solution requires 4 three-input gates and 3 two-input gates.
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55. 7.2 THE DESIGN OF SYNCHRONOUS COUNTERS
Chapter 7 The Design of Sequential Systems
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7.2 THE DESIGN OF SYNCHRONOUS COUNTERS
The maps and equations for the SR solution follow.
S and R are both don’t cares for all three flip flops.
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56. 7.2 THE DESIGN OF SYNCHRONOUS COUNTERS
Chapter 7 The Design of Sequential Systems
6 - 56
7.2 THE DESIGN OF SYNCHRONOUS COUNTERS
S1 = q2’q3 + q2q3’ R1 = q2’q3’ + q2q3 = S1’
= q2’q3’ + q1q2
S2 = q1’q2’q3’ + q1q2’q3 R2 = q1q2 + q2q3’
S3 = q2’ R3 = q2
Even taking advantage of the sharing or using a NOT for R1, this requires more
logic than the D solution.
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57. 7.2 THE DESIGN OF SYNCHRONOUS COUNTERS
Chapter 7 The Design of Sequential Systems
6 - 57
7.2 THE DESIGN OF SYNCHRONOUS COUNTERS
The quick method for JK flip flops,
J1 = q2’q3 + q2q3’ K1 = q3’ + q2
J2 = q1’q3’ + q1q3 K2 = q1 + q3’
J3 = q2’ K3 = q2
Even taking advantage of the sharing or using a NOT for R1, this requires more
logic than the D solution.
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58. 7.2 THE DESIGN OF SYNCHRONOUS COUNTERS
Chapter 7 The Design of Sequential Systems
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7.2 THE DESIGN OF SYNCHRONOUS COUNTERS
This solution requires 8 two-input gates, although the gate for K1 could be
replaced by a NOT gate and the gate for K2 could be eliminated, since by
choosing the don’t cares as 1’s in both places.
K1 = J1’ and K2 = J2
Example 7.6(Cont.)
Assume (state 1 1 0)
q1 = 1, q2 = 1, and q3 = 0
For D flip flops,
D1 = q’2q3 + q2q’3 = = 1
D2 = q’1q’2q’3 + q’1q2q3 + q1q’2q3 = = 0
D3 = q’2 = 0
The system would go to state 4 (1 0 0) on the first clock and continue through
the sequence from there.

59. 7.2 THE DESIGN OF SYNCHRONOUS COUNTERS
Chapter 7 The Design of Sequential Systems
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7.2 THE DESIGN OF SYNCHRONOUS COUNTERS
A state diagram, showing the behavior of the system designed with D or SR
flip flops, including what happens if the system starts in the unused state.
Note that there are no labels on the paths, since there is no input to the
system, and the output is just equal to the state. (Moore system)
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60. 7.3 DESIGN OF ASYNCHRONOUS COUNTERS
Chapter 7 The Design of Sequential Systems
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7.3 DESIGN OF ASYNCHRONOUS COUNTERS
Binary counter are sometimes designed without a clock input.
They are constructed from the same clocked flip flops (typically JK) as synchronous counters.
But each flip flop is triggered by the transition of the previous one. 1 1 B J A J
Count K K
Count : when the Count signal goes from 1 to 0, flip flop A is triggered.
It started out at 0 : it goes to 1
The 0 to 1 transition on the output of A, and thus on the clock input of B, has no effect.
: when the next negative transition on Count occurs, A will go from 1 to 0,
causing the clock input to B to do the same.
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61. 7.3 DESIGN OF ASYNCHRONOUS COUNTERS
Chapter 7 The Design of Sequential Systems
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7.3 DESIGN OF ASYNCHRONOUS COUNTERS
Count A B
There are two things that are different about this timing diagram form the
previous ones.
Since the Count signal is not necessarily a clock, it might be rather irregular.
The delay from the clock is much greater : The first flip flop (A) changes
shortly after the negative edge of the clock, but the second flip flop (B) does
not change until somewhat after A changes.
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62. 7.3 DESIGN OF ASYNCHRONOUS COUNTERS
Chapter 7 The Design of Sequential Systems
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7.3 DESIGN OF ASYNCHRONOUS COUNTERS
Note that the flip flops (BA) go through the sequence 00, 01, 10, 11, and
repeat. Thus, this is a 2-bit counter. 1 1 1 1 D J C J B J A J
Count K K K K
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63. 7.3 DESIGN OF ASYNCHRONOUS COUNTERS
Chapter 7 The Design of Sequential Systems
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7.3 DESIGN OF ASYNCHRONOUS COUNTERS
Notice that A changes one unit of time after the trailing edge of the clock, B
one unit after a trailing edge of A, C after B, and D after C.
Thus, the change in D occurs 4 units after the clock.
Notice also that this counter does go through the sequence 0, 1, 2, 3, 4, 5, 6,
7, 8, 9, 10 and would continue through 11, 12, 13, 14, 15, 0, …
The advantage of the asynchronous counter : the simplicity of the hardware.
There is no combinational logic required.
The disadvantage of the asynchronous counter : speed.
The state of the system is not established until all of the flip flops have
completed their transition, which, in this case, is four flip flop delays.
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64. 7.3 DESIGN OF ASYNCHRONOUS COUNTERS
Chapter 7 The Design of Sequential Systems
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7.3 DESIGN OF ASYNCHRONOUS COUNTERS
Example 7.7
Design an asynchronous base-12 counter using JK flip flops with active
low clears and NAND gates.
The easiest way to do this is to take the 4-bit binary counter and reset it when it
reaches 12.
Thus, the following circuit computes (DC)’ and uses that to reset the counter.
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65. 7.3 DESIGN OF ASYNCHRONOUS COUNTERS
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7.3 DESIGN OF ASYNCHRONOUS COUNTERS
As can be seen from the timing diagram below, the counter cycles
0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, (12), 9
where it remains in state 12 for a short time.
Note that there is a delay from the time that A changes to when B changes
and so forth.
The count is only valid after the last flip flop settles down.
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Continuing Examples
Although the statement of CE6 does not include the term Moore, the
wording of the problem implies a Moore system.
That of CE7 is a Mealy model.
CE6. A system with one input x and one output z such that z = 1 iff x has been 1 for at least three consecutive clock times. x 1 z ?
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The first step in this problem is to determine what needs to be stored in memory.
There are two approaches to step 1 for this problem.
Store the last three inputs.
Store in memory the number of consecutive 1’s.
(A - none , B - one , C - two , D - three or more)
q1* q2* q3* q1 q2 q3
x = 0
x = 1 z 1
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7.4 DERIVATION OF STATE TABLES
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x = 0
x = 1 z A B C D 1
This approach required only four states, whereas the first approach required eight.
The first approach : uses three flip flops.
The second approach : uses only two flip flops.
This is not of a difference.
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The next step in the design process is to reduce the state table, if possible,
to one with fewer states.
That is beyond the scope of this book.
For the first approach, the state assignment has already been made. (flip flops q1, q2, and q3)
The flip flop inputs require no logic for D flip flops.
D1 = q2 D2 = q D3 = x
For JK flip flops.
J1 = q2 J2 = q J3 = x
K1 = q’2 K2 = q’ K3 = x’
For either type of flip flop, one AND gate is needed for z:
z = q1q2q3
For the second approach,
D1 = q1* = xq2 + xq1 or J1 = xq2 K1 = x
D2 = q2* = xq2’ + xq1 or J2 = x K2 = x’ + q1
x = q1q2

70. 7.4 DERIVATION OF STATE TABLES AND STATE DIAGRAMS
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7.4 DERIVATION OF STATE TABLES
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CE7. A system with one input x and one output z such that z = 1 at a
clock time iff x is currently 1 and was also 1 at the previous two
clock times.
Another way of wording this same problem is
CE7#. A Mealy system with one input x and one output z such that z = 1
iff x has been 1 for three consecutive clock times.

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Two approaches for this problem.
For the first approach : only store the last two inputs. (rather than three for the Moore model)
q1* q2* z q1 q2
x = 0
x = 1 1
For the second approach : store in memory the number of consecutive 1’s,
as follows
(A - none, B - one, C - two or more)
That is sufficient information since the output is 1 iff there were previously two
or more 1’s and the present input is a 1.
If the present input is a 0, the next state is A.
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7.4 DERIVATION OF STATE TABLES
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x = 0
x = 1 A B C 1
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7.4 DERIVATION OF STATE TABLES
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Basically, the Moore model output is the same as the Mealy, but delayed by one clock period.
The Mealy model has a glitch when x is still 1 in state C.
The Moore model does not have any false outputs, since z depends only on the
flip flops, all of which change at the same time.
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Example 7.8
Design both a Moore and a Mealy system with one input x and one output z
such that z = 1 iff x has been 1 for exactly three consecutive clock times. x
z-Mealy *
z-Moore
For the Mealy model, (need five states)
A - none, that is, the last input was 0
B - one 1 in a row
C - two 1’s in a row
D - three 1’s in a row
E - too many (more than 3) 1’s in a row

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The state diagram begins like that of the previous solution.
The implementation of this system requires three flip flops.
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For the Moore model,
A state D to indicate exactly three 1’s.
From there, it goes to E on another 1, indicating too many 1’s.
State F is reached on a 0 input; it is the state with a 1 output. q* q
x = 0
x = 1 z A B C D F E 1
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Example 7.9
Design a Mealy system whose output is 1 iff the input has been 1 for three
consecutive clocks, but inputs are nonoverlapping. x z
As in CE7, only three states are needed.
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7.4 DERIVATION OF STATE TABLES
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Example 7.10
Design a Mealy system where the inputs are considered in blocks of three.
The output is 1 iff the input is 1 for all three inputs in a block
That 1 output cannot occur until the third input is received. x z
where the blocks are indicated by extra space. q* z q
x = 0
x = 1 A C B E D G F 1
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But that creates two extra states.
Note that the paths out of C and of E are denoted as X/0.
Input is don’t care.
That path is followed and the output is 0.
Notice that the next state and output sections of the last three rows of the
state table are identical.
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Example 7.11
Design a Mealy system whose output is 1 for every third 1 input.
The initial state, A, is used for no 1’s or a multiple of three 1’s.
When a 0 is received, the system stays where it is, rather than returning to the
initial state, since a 0 does not interrupt the count of three 1’s. x z
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Example 7.12
CE8. Design a Moore system whose output is 1 iff three consecutive 0
inputs occurred more recently than three consecutive 1 inputs. x
z ? ? ?
The initial state S1
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Example 7.13
Design a Mealy system whose output is 1 iff there have been exactly two
1’s followed by a 0 and then a 1.
Assume overlapping is allowed.
Assume overlapping is not allowed.
When a. x z
The underlines indicate the 1101 pattern.
The double underline is not an acceptable pattern since it does not begin
with exactly two 1’s.

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7.4 DERIVATION OF STATE TABLES
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0/0
1/0
1/1
nowhere, last
input = 0
two 1’s
0110
One 1
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There are two interpretations to consider in the nonoverlapping case.
The first is shown as b-1. x b
A second interpretation(perhaps a little far-fetched). x b

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Example 7.14
CE11. Design a Moore model bus controller that receives requests on separate lines, R0 to R3, from four devices desiring to use the bus.
It has four outputs, G0 to G3, only one of which is 1, indicating which
device is granted control of the bus for that clock period.
The low number device has the highest priority, if more than one device
requests the bus at the same time.
The bus controller has five states:
A: idle, no device is using the bus
B: device 0 is using the bus
C: device 1 is using the bus
D: device 2 is using the bus
E: device 3 is using the bus

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The system remains in the idle state if there are no requests.
It goes to the highest priority state when there are one or more requests.
If the idle period is not necessary, the state diagram becomes much more
complex. q q*
G0G1G2G3 R0 1 A E D C B
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A preemptive controller.
Where a high-priority device will take control from a lower priority one, even
if the lower priority one is still using the bus.
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7.4 DERIVATION OF STATE TABLES
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G0G1G2G3 R0 1 A E D C B
Although the state diagram for this version would require the same 20 paths
as was needed for the second version, the logic is much simpler.
The condition for going to state B, from each state is 1XXX(R1), to C is
01XX(R1’R2), to D is 001X(R1’R2’R3), and to E is 0001(R1’R2’R3’R4).
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