1 Operational Amplifiers 1

2 Outlines Ideal & Non-ideal OP Amplifier Inverting Configuration Non-inverting Configuration Difference Amplifiers Effect of Finite Gain and Bandwidth Large Signal Operation DC Imperfections Integrators & Differentiators

3 Operational Amplifiers Components of electronic circuits –Passive components (resistors, capacitors, inductors) –Electronic devices (diodes, transistors) OP Amp –Not electronic device –Treat as the basic circuit element because Well defined, almost ideal terminal characteristics Commercially available, widely used circuit building block

4 OP Amp Circuit Symbol Inverting input Non-inverting input With dc power supplies

5 Function of OP Amp Differential-input, single output amplifier –OP amp responds ONLY to the difference signal Open-loop gain

6 Characteristics of Ideal OP Amp Infinite input impedance –NO input current Zero output impedance –Ideal voltage source at the output Infinite open-loop gain A –Closed-loop configuration ONLY Infinite bandwidth Zero common-mode gain = infinite common-mode rejection

7 Equivalent Circuit of Ideal OP Amp

8 Amplifier Configurations Inverting configuration Non-inverting configuration Negative feedback

9 Equivalent Circuit of Inverting Configuration with Ideal OP Amp

10 Virtual Short Circuit Between Two Inputs DO NOT physically short terminals 1 &2 Hence, Due to the infinite gain assumption,

11 Closed-Loop Gain of Inverting Configuration

12 Input/Output Resistances High R i to get max. overall gain  High R 1  Impractically high R 2 to get high G = -R 2 /R 1 Low R i  Smaller gain & not efficient  Solution is in Example 2.2

13 Effect of Finite Gain A Drop the assumption of “virtual short circuit”

14 G For Finite Gain A … To minimize the effect of finite A, make (extreme case) by selecting the resistors satisfying

15 Weighted Summer

16 Weighted Summer with Coefficients of Both Signs

17 Closed-Loop Gain of Non-Inverting Configuration

18 Effect Of Finite Gain A With finite gain Closed-loop gain becomes

19 Voltage Follower/Buffer Unity-gain amplifier (G = 1) by making In the ideal case, it becomes that

20 Two Different Signals Any two signals can be factorized to two different modes Differential-Mode Component: Common mode input signal: Representations of any two different signals

21 Equivalent Circuit Of Two Input Signals

22 Common/Differential Mode Gains Alternative representation:

23 Common Mode Rejection Ratio (CMRR) Why does not use open-loop OP amp? –Because closed loop gain is (1) finite, (2) predictable, and (3) stable.

24 Ideal OP Amp. Common mode rejection property –Ignores any common signal of two inputs. Gain of input 2 is equal to the inverse gain of input 1 Common mode gain: Differential mode gain: Hence, ideal OP amp has infinite CMRR:

25 Difference Amplifier

26 Common Mode Gain

27 Differential Mode Gain With the conditions for the perfect common-mode rejection: The circuit becomes the difference amplifier satisfying:

28 Differential Input Resistance

29 Instrumentation Amplifier Problem of a single OP amp difference amplifiers –Require high resistance R1 in order to get high input impedance –Results in extremely high resistance R2 in order to get high differential gain Solution –Buffering the two input terminals using voltage followers

30 Circuit For Instrumentation Amp.

31 Disadvantages Of Previous Design 1.Common mode signal is amplified at the first stage OP amp. saturation OR Reduced overall CMRR 2.Require perfect match between two OP amps A 1 and A 2 3.Require perfect match between two resistors

32 Modified Circuit

33 Properties Of Practical OP Amps Finite gain Limited bandwidth Finite (non-zero) common mode gain –Finite CMRR Finite input resistance Non-zero output resistance

34 Freq. resp. of open-loop gain of OP Amp (Unity-gain bandwidth)(Corner frequency)

35 Frequency Response of Inverting Amplifiers From slide 16 DC gain: Corner Freq:

36 Non-Linear Distortion of Large Signal Operation Output voltage saturation Output current limits (about ±20 mA) Slew rate Full-power bandwidth

37 Output Voltage/Current Limits See Example 2.5 in page 94 for exact understanding

38 Slew Rate Limiting Maximum rate of change possible at the output of the real OP amp. Distinct from the finite bandwidth limiting the frequency response. (linear distortion)

39 Step Response to Voltage Follower When V is sufficiently small

40 Full Power Bandwidth Non-linear distortion when Full power bandwidth:

41 DC Imperfections Offset Voltage –1 ~ 5 mA –Depends on Temerature Input Bias and Offset Currents

42 CKT Model with Offset Voltage Data sheet specifies –Typical V OS –Max. V OS –Temp coefficient: μ V/ °C –No polarity (not known a priori)

43 Offset Voltage Effect Output signal is shifted by DC voltage (Vo) –Reduced allowable signal swing

44 Applying Coupling Capacitor Cannot amplify DC or low frequency signal components Form STC high-pass filter with

45 Input Bias & Offset Currents Input offset current: Input bias current: For BJT, I B = 100 nA & I OS = 10 nA For FET, pA

46 DC Output Voltage Due to Bias Currents Problem: Limit R 2  Limit closed loop gain

47 Solution Output voltage becomes By setting

48 Conclusion In order to minimize the effect of the bias currents, make R 3 = [dc resistance at inverting terminal] ac coupled amplifier

49 Inverting Configuration with General Impedances