RD program on hybrids & Interconnects Background & motivation At sLHC the luminosity will increase by a factor 10 The physics requirement on the tracker performance is expected to be the same in the sense that we want to: –Maintain the P T resolution  Approximately the same strip pitch (50  m, 80  m) for the pixel & SCT  In addition sufficient silicon r  layers to match the 200  m/√(36) from the TRT i.e. ~ 2-4 layers with pitch 80  m? –Maintain the  resolution (~1mrad)  Could be achieved by upgrading pixels  400  m  300  m  and/or increase the outer layer radius from ~12cm to ~20cm  Could be achieved by keeping SCT stereo angle of R ~50cm

Background & Motivation continued –In addition we need to maintain the same pattern recognition abilities. This has not yet been simulated and we can only guess at likely solutions –The SCT specification was based on a strip occupancy of 0.5% from pile-up and 1.5% inside b-jets. Using the SCT stand-alone this resulted in fake track rates of  ~6% at 20mrad  ~12% at 100mrad –For sLHC, a safe solution would be to maintain the strip occupancy by shortening the strips to ~1cm.  Is this necessary - the number of ghosts varies as L 2 and ~3cm maybe OK with 40mrad stereo  Instead of a double stereo layer with strip length 1cm should consider a single layer of 5mm strips for pattern recognition or ~2mm strips to give the required z- resolution

Proposed goals of R&D 1.Investigate the use of stripcels as part of the upgraded ATLAS tracking system. Fix requirements and specification for stripcel size 2.Define a target geometry for a stripcel module 3.R&D towards a double-sided silicon MCM-D hybrid with electrical connections on both sides –Minimise area, material –Understand thermal issues 4.Developing in-house expertise to bump bond ASICs to MCM-D, ASICs to sensors, and 3 layer stacks. 5.R&D on putting vias through CMOS readout ASICs allowing them to be contacted and powered from the back-side 6.Prototype a short strip module

Vision to start discussion –DC coupled sensor with short strips 2mm – 10mm Could be AC subject to a smart idea on biasing –Bump-bonded pixel like ASICs –Challenges ASIC IO Cooling ASICs (bump-bonded Hybrid (2 options) Sensor

Stripcel coverage Pixel chip is 9x800 mm wide = 7.2mm + 0.2mm = 7.4mm  1 double row of readout would be 1.0mm wide but the chip length needs to be reduced from 11mm to 8mm which increases width.  I have tried to estimate the area of wafer covered as a function of stripcel length For short strips need to investigate include additional routing on the ASIC or sensor.

Vision to start discussion continued –Manage ASIC IO Vias in ASIC Silicon MCMD 3 layer stack

Information – ATLAS pixel module schematics Notes: – Pixel module is 2 chips wide -Uses on detector routing

Proposed goals of R&D 1.I see the above as a starting point for a major work program. 2.Many basic parameters need to be fixed –Stripcel specification –Module topology –Thermal issues 3.Basic R&D on vias and MCMDs could start now in parallel with optimising specification 4.There is an expanding interest and effort in this technology which we need to understand and benefit from –MPI are working with IZM to develop small pixels for the ATLAS Upgrade –Many people are interested in 3D for x-ray imaging –IMEC EU project

3D circuits - Industry

3D circuits – for ATLAS pixel upgrades

From Ray Yarema (3D program at FNAL)