1. Module Integration Issues Changing Occupancy Requirements Current Module Proposals Module Design Issues Conclusions Phil Allport Module Integration Working Group

2. Relevant parameters for us in the two scenarios  Bunch spacing: 25 ns50 ns  Rms bunch length: 7.55 cm14.4 cm  Long. Profile: GaussFlat  Luminous region: 2.5 cm3.5 cm  Peak lumi: 15.5 10 34 8.9 10 34  Events crossing: 296403  Lumi. Life time: 2.1 h5.3 h  Effective lumi : 2.4 10 34 2.3 10 34 (10 h turn around)  Effective lumi: 3.6 10 34 3.1 10 34 (5 h turn around) 25 ns small ß50 ns long bunch

3. Pixels (50  m  400  m): 3 barrels, 2×3 disks 4.7cm < r < 20cm Pattern recognition in high occupancy region Impact parameter resolution (in 3d) Radiation hard technology: n + -in-n Silicon technology, operated at -6°C Strips (80  m  12 cm) (small stereo angle): “SCT” 4 barrels, 2×9 disks pattern recognition 30cm < r < 51cm momentum resolution p-strips in n-type silicon, operated at -7°C TRT 4mm diameter straw drift tubes: barrel + wheels 55cm < r < 105cm Additional pattern recognition by having many hits (~36) Standalone electron id. from transition radiation Current Inner Tracker Layout r=30cm 0.61% Mean Occupancy in Innermost Layer of Current SCT Pixels: 2 m 2, ~80M channels SCT: 60 m 2, ~6.3M channels TRT straws: ~400k channels ID TDR

4. 4+3+2 (Pixel, SS, LS) – “Liverpool” Strawman

5. Pixels: 24cm Layer: Short (3cm)  -strips (stereo layers): Long (12 cm)  -strips (stereo layers): r=5cm, 12cm, 18cm, r=24cm r=32cm, 46cm, 60cm r=75cm, 95cm z=±40cm z=±40cm/100cm z=±100cm z=±190cm Strawman 4+3+2 (cf 3+4+2 before) Layout Implications Including disks this leads to: Pixels: 1.7 m 2, ~120,000,000 channels 24cm layer: 1.2/3m 2, 90/200,000,000 channels Short (3cm) strips: 60 m 2, ~25,000,000 channels Long strips: 100 m 2, ~14,000,000 channels Occupancy vs radius (230 pile-up) Problem: 3+4+2 with occupancy > 1% (27cm had 1.7%)

6. With safety factor of two, design short microstrip layers to withstand 10 15 n eq /cm 2 (50% neutrons) Outer layers up to 4×10 14 n eq /cm 2 (and mostly neutrons) Quarter slice through ATLAS inner tracker Region, with 5cm moderator lining calorimeters. Fluences obtained using FLUKA2006, assuming an integrated luminosity of 3000fb -1. Radiation Levels → → Issues of thermal management and shot noise. Silicon looks to need to be at ~ -25 o C (depending on details of module design). → → High levels of activation will require careful consideration for access and maintenance. Issues of coolant temperature, module design, sensor geometry, radiation length, etc etc all heavily interdependent.

7. SLHC Module - A Proposal Y. Unno Presentation 7/12/06 http://indico.cern.ch/conferenceDisplay.py?confId=a063014 Presented at the Oct. workshop at CERN One module with 124x64mm 2 sensor –Segmented into 1, 2, and 4 striplets –Wrap-around hybrids with 1, 2, and 4 rows of ASIC’s

8. SLHC module Edge “stay-clear” region (10 mm) should not have openings for strips/bias rings High/Low position of the modules in the right figure Tilt angle of 16 deg. is comfortable for roofing Note: available TPG size, 100mm x <150mm

9. SLHC - Full Area Baseboard Model –LHC SCT barrel module –Full area baseboard=2D Silicon –w=64mm, t=300µm, 2-sides Baseboard: –TPG1400, t=400µm –k=1400 W/m/K Hybrid: –CC bridge, t=300µm –k=650 W/m/K Electronics heat –4 rows of ASIC’s –28W/12cm Cooling –Single-side cooling –Sensor to Coolant:∆T=10 ºC (@28W)

10. SLHC - 2D Model Fluence 3000fb -1 x SF2 –Cooling pipe wall temp. -30 ºC Hybrid=28W –Hottest sensor temp. -19 ºC (due to mainly ASIC’s heat (28W)) –x6 safety for thermal runaway –To get -27 ºC at sensor, cooling wall to be -38 ºC Hybrid=42W –Hottest temp. -14 ºC –>x3 safety for thermal runaway –To get -27 ºC at sensor, cooling wall to be -43 ºC Comments on double-side cooling –Equivalent to single-side cooling of 1/2 width –Cooling contact ∆T x1/2=5 ºC –Heat per cooling x1/2, thermal resistance x1/2, total x1/4, I.e.,sensor could be 13 ºC higher –More material –Leakage current x4 –HV power x8 larger!! Nominal heat flux – –Assuming V bias =800V – –1030 µW/mm^2 at 0 ºC (*) Shorter cooling contact by x3/4 in reality is compensated in 2xQnominal/Qmax ~ 0.7

11. Sensor sizes in 150 mm wafer n.b. 124.68 mm implies 3cm strips; 103.39 implies 2.4cm strips (assuming 4 rows on each sensor)

12. Strip sensor parameters DRAFT Gap between strip ends might be sensitive as it is as same as between strips

13. Occupancy and sensor size Pavel Nevski

14. Implications of sensor size (Straight) Track incident angles r=30cm 12x6cm 2 10x10 cm 2 Angle to sensor6˚9.4˚ Angle to drift (tilt=16˚)22˚25.4˚ –Need to evaluate the drop of efficiency(?)

15. Implications of sensor size These are calculations done by Y. Unno Not shown in the PO meeting Materials for discussion 50ns - 400 pileup events

16. Implications of sensor size 12cmx6cm-6chips 10cmx10cm-10chips

17. SLHC module - Wide sensor A worst case(?) study

18. SLHC module - Worst case? Original model –Wide sensor (104 mm x 94 mm) –Outer region –9 ASIC’s/row/side x 2 rows x 2 sides –36 ASIC’s –42W/104mm Comments on wide model –Remember the electrical instability of ABCD3T ASICs –2x6 chips/row was marginal

19. SLHC module - Optimization Modified module –Extending hybrid substrate (CC) closer to cooling area –Thermally insulating the far side of the hybrid feet

20. SLHC module - Optimization Even with TPG=0.3 mm (nominal 0.4mm) –~x3 safety, sensor temp. -20 °C –Penalty: hottest chip temp. ~5 °C up

21. Pileup Events/Readout - 230

22. LBL Stave Proposal; Carl Haber

30. Schematic 2 Edge Cooling Contact 6 Chip Wide Stave Current Barrel Module Concept to avoid gluing to silicon strip surface Sensors 4 rows of 3cm mini-strips (Liverpool Stave Proposal)

31. Schematic 2 Edge Cooling Contact 9 Chip Wide Stave Current Barrel Module Concept to avoid gluing to silicon strip surface Sensors 4 rows of 2.5cm mini-strips (Liverpool Stave Proposal)

32. Issues for Module Layout Design External Constraints on Module Design Final required granularity→ pitch → ASIC power density Required spatial resolution (both r-φ and z) Stereo angle / ambiguities / pattern recognition Track trigger requirements Lowest feasible coolant temperature→ allowed ΔT Mechanical and thermal stability of external supports Minimum required natural frequency Allowed total radiation length Required hermeticity of each tracking layer Total cost, power and cable budgets

33. Issues for Module Layout Design Internal Constraints on Module Design Automation of construction, ease of rework and likely yield Number of separate units per radial layer Mechanical tolerances, metrology precision and required rigidity Risk: similarity to existing solutions (not just in ATLAS) Can components be safely glued onto sensor segmented surface ASIC layout, maximum # ASICs per hybrid, can we dispense with fan-ins? Total cost of components, construction and testing Stereo (rotate sensor or different mask design) Wrap-around or r-φ / stereo treated independently Compatibility of possible forward designs Maximise common components at all radii and on disks

34. Comments on Module Options I expect both main options can be made to work Single sensor size units read-out individually and mounted to structures providing mechanical support, defining sensor position, providing cooling and carrying some electrical/optical services. Similar approach to current ATLAS SCT Staves of ~1m length with integrated cooling + electrical connections, providing inherent mechanical stability and (depending on external support structure) required rigidity Similar approach in some respects to CMS rods

35. Some Urgent Questions External Issues Changes in likely occupancy at start of SLHC runs, make a decision urgent on required sense element dimensions. If < 80μm×3cm for strips, either reduce pitch (problem <70μm with ABCD-like layout and connections needed to ASIC sides) or strip length (what is the minimum feasible hybrid width) ) 30cm inner radius, given width ±3cm (±4.5cm) will give track angle range up to ±6 o ( ±8.5 o ) (nb Lorentz angle for electrons is 16 o ) Coolant temperature and allowed ΔT to silicon Total allowed power budget: is there a limit? Hermeticity: how important is 100% and is this achievable (must there anyway be gaps between rows of strips in the sensor). Stability, natural frequency, sag … Cylinder looks to have natural advantages, what concerns does the stave solution still need to address, is a hybrid solution possible?

36. Some Urgent Questions Internal Issues Note best sensor options look to be 12×6cm or 10×9cm. 10×9cm fits better with 2.5cm length strips. If 72μm pitch could reduce sense area by ~25%, giving 10 chip wide module. 12×6cm allows to stick with 6 chip wide solution as at present but uses 20% less of 6” silicon wafer area. Adhesion of components on sensitive surface of silicon: What tests (thermal cycling, radiation etc) would convince sceptics? For a given channel density, what ΔT is implied by each module option. How much additional material does each require to achieve the same ΔT. Required mechanical tolerances likely to determine possible degree of automation in assembly and is related to rework risks with larger units (staves). (Very tight tolerances were a significant yield issue for the current modules, although overall yields were still good).

37. Conclusions The new occupancy requirements lead to worries about the robustness of the previous baseline. A combination of starting at 32cm rather than 27cm and reducing the sense area by 25% is proposed (98.99mm x 98.99 mm square, strip segment of 2.4cm x 75.6µm, to be specific) but it does not quite deliver <1% occupancy in the inner layer of the new 4+3+2 “strawman” layout. If we accept the sensors need to be cooled to -25 o C, what are the coolant options? If the pixels must be cooler, is it anyway assumed that the whole SCT uses the same cooling solution? The schedule requires us urgently to fix the sensor and ASIC geometrical specifications and get to the next stage of prototyping for both major module concepts. Mechanical/stability/sag and assembly (glue) concerns for stave concepts need to be properly articulated and thoroughly studied. Is a combined solution, taking the best of both concepts, conceivable?

38. Steering Group http://indico.cern.ch/conferenceDisplay.py?confId=11546 Project Office http://indico.cern.ch/conferenceDisplay.py?confId=11648 Module Integration http://indico.cern.ch/conferenceDisplay.py?confId=11902 ABC-next http://indico.cern.ch/conferenceDisplay.py?confId=11907 Proposals and Expressions of Interest https://edms.cern.ch/cedar/plsql/navigation.tree?cookie=6024064&p_top_id=1 349898803&p_top_type=P&p_open_id=1084168533&p_open_type=P