© S.N. Sabki CHAPTER 6: MOSFET & RELATED DEVICES CHAPTER 6: MOSFET & RELATED DEVICES

© S.N. Sabki MOSFET and Related Devices 6.1 The MOS diode 6.2 MOSFET fundamentals 6.3 MOSFET scaling 6.4 CMOS and BiCMOS 6.5 MOSFET on insulator 6.6 MOS memory structures 6.7 The power MOSFET

© S.N. Sabki THE MOS DIODES Figure 6.1. ( a ) Perspective view of a metal-oxide-semiconductor (MOS) diode. ( b ) Cross-section of an MOS diode.

© S.N. Sabki

Figure 6.2. Energy band diagram of an ideal MOS diode at V = 0. THE MOS DIODES (cont.)

© S.N. Sabki

KEYWORDS : a)Work Function, : Energy difference between the Fermi level and the vacuum level. b) Electron affinity, : Energy difference between the conduction band edge and the vacuum level in the semiconductor. c) : Energy difference between the Fermi level E F and the intrinsic Fermi level E i

© S.N. Sabki An ideal MOS is defined as follows: a)At zero applied bias, the energy difference between the metal work function (q  m ) and the semiconductor work function (q  s ) is zero or the work function difference (q  ms ) is zero # The energy band is flat (flat band condition) when there is no applied voltage b) The only charges that exist in the diode under any biasing conditions are those in the semiconductor and those with equal but opposite sign on the metal surface adjacent to the oxide. c) There is no carrier transport through the oxide under direct current (dc) - biasing condition or the resistivity of the oxide is infinite. (1) THE MOS DIODES (cont.)

© S.N. Sabki a)ACCUMULATION CASE : -V<0 is applied to the metal plate, holes will be induced at the SiO 2 – Si interface. -Bands near the semiconductor surface are bent upward. It cause an increase in the energy E i -E F which in turn gives rise to an enhanced concentration and accumulation of holes near the oxide- semiconductor interface -No current flows. b) DEPLETION CASE : -V>0 is applied, the energy bands near the semiconductor surface are bent downward. -Holes (majority carriers) are depleted. THE MOS DIODES (cont.) ENERGY BAND DIAGRAMS AND CHARGE DISTRIBUTIONS OF AN IDEAL MOS DIODE

© S.N. Sabki c) INVERSION CASE : Larger positive voltage applied, energy bands bend downward even more so the E i at the surface crosses over the Fermi level. The positive gate voltage starts to induce excess electrons at the SiO 2 – Si interface. Electrons greater than holes, thus the surface is inverted. THE MOS DIODES (cont.) Carrier density (holes) depends on energy difference

© S.N. Sabki Figure 6.4. Energy band diagrams at the surface of a p -type semiconductor. The surface depletion region THE MOS DIODES (cont.)

© S.N. Sabki  (electrostatic potential)=0 (in bulk)  s (surface potential)=  (at s/c surface) Electron concentration Hole concentration (2) (3) Expressed as a function of  See eq. (4) & (5) (4) (5)  is positive when the band is bent downward (6) (7) Densities at the surface

© S.N. Sabki The following regions of surface potential can be distinguished:  s  0Accumulation of holes (bands bend upward)  s =0Flat-band condition  B  s  0Depletion of holes (bands bend downward)  s =  B Midgap with n s = n p = n i (intrinsic conc.)  s >  B Inversion (bands bend downward) (7)  as a function of distance (1D poisons eq.)  s (x): charge density per unit volume  s : dielectric permittivity

© S.N. Sabki When the semiconductor is depleted to a width of W and the charge within the semiconductor is given by, (8) (9) Maximum width of the surface depletion region W m : Note: Potential distribution = one sided n + -p junction The surface is inverted whenever  s  B n s (e conc at surface)= n A (substrate impurity concentration) (10) Electrostatic potential at surface depletion region:

© S.N. Sabki Figure 6.5. Maximum depletion-layer width versus impurity concentration of Si and GaAs under strong-inversion condition. Example For an ideal metal-SiO 2 -Si diode having N A =10 17 cm -3, calculate the maximum width of the surface depletion region Solution: At room temp. kT/q=0.026 and n i =9.65x10 9 cm -3, the dielectric permitivity of Si is 11.9 x 8.85 x F/cm

© S.N. Sabki No work function differences – applied voltage appear partly across oxide & across semiconductor Potential across the oxide Field in the oxide Charge per unit area Oxide capacitance per unit area VoVo oo QSQS CoCo Ideal MOS Curves (a) Band diagram of an ideal MOS diode. (b) Charge distributions under inversion condition. (c) Electric field distribution. (d) Potential distribution

© S.N. Sabki C Total capacitance of MOS diode C o Oxide capacitance C j Semiconductor depletion-layer capacitance W Width of depletion  o Permittivity in vacuum  ox Insulator permittivity ( a ) High-frequency MOS C-V curve showing its approximated segments (dashed lines). Inset shows the series connection of the capacitors. ( b ) Effect of frequency on the C-V curve. 2 Threshold voltage: Minimum value of total capacitance:

© S.N. Sabki The SiO 2 – Si MOS diode  Metal-SiO 2 -Si : most extensively studied  Work function difference q  ms  0 (for metal electrodes)  Work function semiconductor q  s (Energy difference: Between vacuum level – Fermi level)  Work function metal q  m  difference : q  ms  (q  ms - q  s )  Aluminum : q  m = 4.1eV  Polysilicon : n+ q  m = 4.05eV p+ q  m = 5.05eV Work function difference as a function of background impurity concentration for Al, n +-, and p + polysilicon gate materials.

© S.N. Sabki ( a ) Energy band diagram of an isolated metal and an isolated semiconductor with an oxide layer between them. ( b ) Energy band diagram of an MOS diode in thermal equilibrium.  To construct energy band diagram (in the figure)  In the isolated metal & semiconductor – all bands are flat  At thermal equilibrium: constant Fermi level & continuous vacuum level.  At thermal equilibrium:  metal  +ve charge  semiconductor surface  –ve charge  To get ideal flat band: apply a voltage = q  ms  So apply –ve voltage V FB to metal  flat band voltage ( V FB =  ms )

© S.N. Sabki Interface Traps & Oxide Charges  MOS diode is affected by charges in the oxide & traps in the SiO 2 -Si interface  Classifications of traps & charges:  Interface-trapped charge  Fixed oxide charge  Oxide trapped charge  Mobile ionic charge  Interface trapped charge Q it  due to SiO 2 -Si interface properties & chemical composition in the interface  Location: SiO 2 -Si  Interface trap density (number of interface traps per unit area & per eV)  in  100  the interface trap density is an order of magnitude smaller than  111 

© S.N. Sabki  Oxide-trapped charges, Q ot  Associated with defects in SiO 2  The charges can be created (Eg. by X-ray radiation or high energy electron bombardment) – traps are distributed inside the oxide layer.  Can be removed by low temperature annealing  Mobile ionic charges, Q m  Eg. Sodium & alkali ions – mobile under raised-temperature (Eg. >100 o C) & high field operations.  Stability problem in semiconductor devices operated under high bias & high temperature conditions  Mobile ion charges move back & forth through the oxide layer  cause shifts of CV curves along voltage axis  Mobile ions have to be eliminated Fixed charge, Q f  Location: within 3nm of the SiO 2 -Si interface  The charge is fixed – cannot be charged or discharged  Q f is generally +ve & can be regarded as a charge sheet located at the SiO 2 -Si interface

© S.N. Sabki Effect of a sheet charge within the oxide. ( a ) Condition for V G = 0. ( b ) Flat-band condition.  Evaluate the effective net charges per unit area (C/cm 2 ) on the flat band voltage  Consider a +ve sheet charge per unit area Q o within the oxide  induce –ve charges (partly in metal, partly in semicond.) (fig. (a))  Resulting field distribution  assumed that there is no work function difference ( q  ms =0 )  To reach a flat band condition (no charge induced)  apply –ve voltage to metal (fig. (b))  As –ve voltage increases  more –ve charges on the metal  electric field distribution shift downward until the electric field is zero (at surface)  Area contained under the electric field distribution corresponds to the flat-band voltage V FB :

© S.N. Sabki Q o Density of the sheet charge x o Location within the oxide  When sheet charge very close to metal  if x o =0 : induce no charges, no effect on the flat band voltage  When Q o very close to semiconductor  x o = d : it will exert its max influence, give rise to a flat band voltage:  Arbitrary space charge distribution within the oxide:  (x) : volume charge density in the oxide  ot (x) : volume charge density for oxide-trapped charges  m (x) : volume charge density for mobile ionic charges If q  ms  0 & interface-trapped charges is negligible  experimental C-V curve will be shifted from the ideal theoretical curve by an amount : Important!

© S.N. Sabki Effect of a fixed oxide charge and interface traps on the C-V characteristics of an MOS diode.

© S.N. Sabki MOSFET

MOSFET

MOSFET FUNDAMENTALS Perspective view of a metal-oxide-semiconductor field- effect transistor (MOSFET). IGFET : insulating-gate field-effect transistor MISFET : Metal-insulator-semiconductor field-effect transistor MOST : Metal-oxide-semiconductor transistor Basic device parameters: Channel length, L, (distance between two metallurgical n+ -p junction) Channel width, Z Oxide thickness, d Junction depth, r j Substrate doping, N A

© S.N. Sabki BASIC OPERATION 2) Low Drain Voltage : When a small drain voltage applied, electrons will flow from the source to the drain through the conducting channel. The channel acts as a resistor, and the drain current I D proportional to the drain voltage. Current flow can be controlled by using gate voltage. This create a linear region in IV curve 1)When V G =0 : Source and drain electrodes correspond to two p-n junctions connected back to back. Zero current flow from source to drain ideally. This create an inversion layer which will be a threshold voltage, V t prior current flow. When small positive voltage applied to gate, V G the central MOS structure is inverted and a channel is formed. Current begin to flow.

© S.N. Sabki 3) Onset On Saturation : If V D increases, the inversion layer width reduces as the V D is larger than V G. At one point, the inversion layer will disappear as the V D is enough to compensate the inversion layer strength. This point is called pinch off point and the V D saturates. 4) Beyond saturation : Beyond pinch off point, maximum number of electron will flow from source to drain. Therefore, the current saturation occur. The current flow now controlled by V G and independent of V D. The major changes is the reduction of channel length.

© S.N. Sabki Derivation of basic characteristics under following conditions: a) The gate structure correspond to an ideal MOS diode – no interface traps, fixed-oxide charges or work function differences. b) Only drift current considered c)Carrier mobility in the inversion layer is constant d)Doping in the channel is uniform e)Reverse leakage current is negligibly small f)The transverse field created by the gate voltage in the channel is much larger than the longitudinal field created by the drain voltage g)The gradual-channel approximation – the charges contained in the surface depletion region of the substrate are induced solely from the field created by gate voltage

© S.N. Sabki Figure ( a ) MOSFET operated in the linear region. ( b ) Enlarged view of the channel. ( c ) Drain voltage drop along the channel. Q S : Total charge induced in the semiconductor per unit area y : distance from the source  S (y) : surface potential at y C o =  ox /d : gate capacitance per unit area

© S.N. Sabki Q n : charge in the inversion layer per unit area Q s : total of Q n Q sc : charge in surface depletion region per unit area  we can obtain Q n Refer fig. 16(c)

© S.N. Sabki Conductivity of the channel at y: Channel conductance (constant mobility) : Channel resistance of an elemental section dy: Voltage drop across the elemental section: I D independent of y

© S.N. Sabki Figure Idealized drain characteristics of a MOSFET. For V D  V D sat, the drain current remains constant.  For a given V G : I D increases linearly with V D then saturated  The dashed line : locus of the drain voltage V Dsat ( I D approach a max value)

© S.N. Sabki Consider linear and saturation regions (for small V D ) for Threshold voltage V T : Channel conductance g D : Transconductance g m :

© S.N. Sabki  Pinch-off point : V D increased to a point that charge Q n (y) in the inversion layer at y=L  number of mobile ē at the drain are reduced drastically  At this point V D & I D  V Dsat & I Dsat  V D > V Dsat  saturation region

© S.N. Sabki TYPES OF MOSFET Cross section, output, and transfer characteristics of four types of MOSFETs.

© S.N. Sabki TRESHOLD VOLTAGE Figure Calculated threshold voltage of n - channel ( V Tn ) and p -channel ( V Tp ) MOSFETs as a function of impurity concentration, for devices with n +-, p + – polysilicon, and mid-gap work function gates assuming zero fixed charge. The thickness of the gate oxide is 5 nm. NMOS, n -channel MOSFET; PMOS, p -channel MOSFET.

© S.N. Sabki MOSFET applied in the semiconductor industry for : a) VLSI Circuits b) Memory Devices ( DRAM, SRAM, Nonvolatile Memory) c) CMOS Digital Circuit d) Microprocessors Advantages of MOSFET : a) In CMOS, perfect zero current when input switch off. Good logic ‘1’ and logic ‘0’ condition. b) Ability to scale down in size. (Channel length, width, area) c) Ability to control threshold voltage when device shrink. Quick switching. d) Oxide layer between gate and channel prevent DC flow – Power Consumption. e) Low power consumption allow more components per chip surface area. MOSFET APPLICATION

© S.N. Sabki DISADVANTAGES OF MOSFET Reduces V T makes MOSFET could not switched off – weak inversion layer. Interconnect capacitance between wires – device miniature reduces. Heat production impact – shrink device size, increasing device quantity. Thin oxide requirement – gate oxide tunneling leakage problem. Increased process fabrication steps – complex circuit design.

© S.N. Sabki Next Lecture: CHAPTER 8: MICROWAVE DIODES,QUANTUM- EFFECT, AND HOT ELECTRON DEVICES

© S.N. Sabki ATTENTION… Compile your Mini Project results Mini Project Report Submit Mini Project Report: On 19 th Sep 2007 (Wednesday) during lecture Report should be in 5 pages only Follow the format!! Mini Project Presentation Mini Project Presentation: On 24 th & 25 th Sep 2007 during lab session Prepare your slides! Present in 15 minutes only